Abstract: A semiconductor embedded module 1 of the present invention has a configuration in which a semiconductor device 20, which is an electronic component such as a semiconductor IC (die) in a bare chip state, is embedded in a resin layer 10 (second insulating layer). In the semiconductor device 20, a redistribution layer 22 is connected to land electrodes. A protective layer 24 (first insulating layer) is provided on the redistribution layer 22, and is provided with openings such that external connection pads P of the redistribution layer 22 are exposed. Also, the resin layer 10 is formed to cover the protective layer 24, and vias V are formed at the positions of the respective external connection pads P of the redistribution layer 22. The grinding rate of the resin layer 10 is larger than that of the protective layer 24.

Abstract: A typical post-out flow data path at the IC Fabrication has following major components of software based processing—Boolean operations before the application of resolution enhancement techniques (RET) and optical proximity correctin (OPC), the RET and OPC step [etch retargeting, sub-resolution assist feature insertion (SRAF) and OPC], post-OPCRET Boolean operations and sometimes in the same flow simulation based verification. There are two objectives that an IC Fabrication tapeout flow manager wants to achieve with the flow—predictable completion time and fastest turn-around time (TAT). At times they may be competing. An alternative method of providing target turnaround time and managing the priority of jobs while not doing any upfront resource modeling and resource planning is disclosed. The methodology systematically either meets the turnaround time need and potentially lets the user know if it will not as soon as possible.

Abstract: A group of models are developed to predict printed contour deviations relative to the corresponding layout edges for different classes of layout topologies. A plurality of calibration layouts with topologies belonging to a class of layout topologies are used to generate a model for the class of layout topologies. A standard least square regression is modified for model creation. The model error may be monitored dynamically.

Abstract: An LED lamp 10 that is a light source device includes a light emitting module 14, a body 12 that is a first thermal dissipation member onto which the light emitting module 14 is attached, a circuit unit 22 for lighting the light emitting module 14, and a case 24 that is a second thermal dissipation member that has the circuit unit 22 housed therein, and a thermal insulation member 20 is inserted between the body 12 and the case 24.

Abstract: Light source apparatus whose front cover can be removed easily and which can be attached to socket easily even if the base is screw-in type. The light source apparatus includes: cylindrical body 10 having opening 11; light-emitting module 20 housed in body 10; and front cover 40 attached to opening-side end of body 10. Ring-like flange 14 is provided at opening-side end 10a of body 10. A plurality of claws 44 are provided at circumferential edge 43 of front cover 40. Front cover 40 is fitted to opening-side end 10a of body 10 such that flange 14 is covered by circumferential edge 43 of front cover 40. Flange 14 is provided with at least one stopper face 15a which, when it is in contact with at least one claw 44, restricts front cover 40 from rotating around cylindrical axis J of body 10.

Abstract: Light source apparatus whose front cover can be removed easily and which can be attached to socket easily even if the base is screw-in type. The light source apparatus includes: cylindrical body 10 having opening 11; light-emitting module 20 housed in body 10; and front cover 40 attached to opening-side end of body 10. Ring-like flange 14 is provided at opening-side end 10a of body 10. A plurality of claws 44 are provided at circumferential edge 43 of front cover 40. Front cover 40 is fitted to opening-side end 10a of body 10 such that flange 14 is covered by circumferential edge 43 of front cover 40. Flange 14 is provided with at least one stopper face 15a which, when it is in contact with at least one claw 44, restricts front cover 40 from rotating around cylindrical axis J of body 10.

Abstract: Various techniques are disclosed to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes associating segmented wires of the PLD with a plurality of wire index values based on connections identified by interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.

Abstract: The present invention aims to provide a light source apparatus including a small case housing therein a circuit unit including a tall electronic part and a wide mounting substrate. A light source apparatus 1 comprises: a light emitting module 20 as a light source; a circuit unit 60 including a plurality of electronic parts 61a-61f for lighting the light emitting module 20 and a mounting substrate 62 on which the electronic parts 61a-61f are mounted; and a case 70 that is tubular and has an opening at one end thereof, the case 70 housing therein the circuit unit 60. The mounting substrate 62 is held by the case 70 so as to be slanted with respect to a tube axis of the case 70 and not to intersect the tube axis.

Abstract: An LED lamp 10 that is a light source device includes a light emitting module 14, a body 12 that is a first thermal dissipation member onto which the light emitting module 14 is attached, a circuit unit 22 for lighting the light emitting module 14, and a case 24 that is a second thermal dissipation member that has the circuit unit 22 housed therein, and a thermal insulation member 20 is inserted between the body 12 and the case 24.

Abstract: Lamp realizing high brightness without increase in size, including: case 3 that is in conical shape, wherein LEDs 37 are installed on inner surface of bottom 5 of case 3; lens 13 that is smaller than case 3 in size and positioned in case 3 such that light emission face 63 of lens 13 is on opening side of case 3; cover 15 that is installed to cover opening of case 3 so that light emitted from face 63 is extracted to outside of lamp; base member 17 that is hollow inside and attached to outer surface of bottom 5 of case 3 to project toward outside; and lighting circuit 23 that receives electricity via base member 17, and causes LEDs 37 to emit light. Electronic parts 49, 51 and 99 constituting lighting circuit 23 are arranged in distribution in spaces of case 3 and base member 17.

Abstract: A light source apparatus that can be assembled and disassembled easily. A light source apparatus 100 includes: a body 120 housing a light-emitting module 110; and a front cover 130 attached to an opening portion 121 of the body 120 and including a light emission window 131 for allowing light emitted from the light-emitting module 110 to go outside. The opening portion 121 is provided on a front side of the body 120. The front cover 130 includes a plurality of engaging claws 134a through 134f and is attached to the body 120 when the engaging claws 134a through 134f engage with a claw receiving portion 124 provided in an outer surface of the body 120.

Abstract: A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD). In one embodiment, the method includes mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; identifying a segmented wire connected to the master switch; mapping the identified segmented wire to a second master wire; and mapping the second master wire to the second routing graph wire.

Abstract: A group of models are developed to predict printed contour deviations relative to the corresponding layout edges for different classes of layout topologies. A plurality of calibration layouts with topologies belonging to a class of layout topologies are used to generate a model for the class of layout topologies. A standard least square regression is modified for model creation. The model error may be monitored dynamically.

Abstract: Various techniques for referencing components of a programmable logic device (PLD) are provided. In one example, a method of referencing wires of a routing graph of a PLD is provided. The routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD. The method includes maintaining a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively. The method also includes identifying a first one of the routing graph wires. The method further includes mapping the first routing graph wire to a second one of the routing graph wires using at least one of the master wires.

Abstract: A semiconductor IC-embedded module 100 comprises a multilayer substrate 101 having first and second insulating layers 101a and 101b, and a controller IC 012 and memory IC 103 that are embedded in the multilayer substrate 101. A wiring layer 104 is formed as an internal layer in the multilayer substrate 101. Part of the wiring layer 104 constitutes a bus line 104X. The controller IC 102 or memory IC 103 is embedded in the second insulating layer 101b. First and second ground layers 105a and 105b are provided respectively in the first and second insulating layers 101a and 101b. The effect of noise generated by bus lines is reduced, and an additional reduction in noise and a decrease in size and thickness are achieved by laying out bus lines that connect the semiconductor ICs so that distances are minimized.

Abstract: Various techniques are described to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes identifying a plurality of interface templates corresponding to tiles of the PLD. The PLD comprises a plurality of segmented wires arranged in a plurality of tiles. Each interface template corresponds to at least two adjacent tiles of the PLD and identifies connections between segmented wires of the corresponding adjacent tiles. The method also includes associating the segmented wires of the PLD with a plurality of wire index values based on the connections identified by the interface templates. The method further includes identifying a plurality of composite wires according to the wire index values. Each composite wire comprises a set of the segmented wires associated with a corresponding one of the wire index values. The composite wires are adapted to interconnect programmable logic blocks of the PLD.

Abstract: A hard disk drive is provided with a platter, a spindle motor for driving the platter, an arm with a magnetic head attached to a distal end thereof, a voice coil motor for driving the arm, a first circuit substrate, and a drive casing for accommodating and electrically shielding the platter, spindle motor, arm, voice coil motor, and first circuit substrate. The first circuit substrate has a multilayer substrate, a plurality of digital ICs that are embedded as bare chips in the multilayer substrate, and a bus line for connecting the digital ICs. The digital ICs are disposed in a mutually horizontal configuration.

Abstract: A semiconductor embedded module 1 of the present invention has a configuration in which a semiconductor device 20, which is an electronic component such as a semiconductor IC (die) in a bare chip state, is embedded in a resin layer 10 (second insulating layer). In the semiconductor device 20, a redistribution layer 22 is connected to land electrodes. A protective layer 24 (first insulating layer) is provided on the redistribution layer 22, and is provided with openings such that external connection pads P of the redistribution layer 22 are exposed. Also, the resin layer 10 is formed to cover the protective layer 24, and vias V are formed at the positions of the respective external connection pads P of the redistribution layer 22. The grinding rate of the resin layer 10 is larger than that of the protective layer 24.

Abstract: A module with embedded semiconductor IC of the present invention includes a first resin layer, a second resin layer, post electrodes passing through the first and second resin layers, and a semiconductor IC mounted as embedded between the first resin layer and the second resin layer. Stud bumps are formed on land electrodes of the semiconductor IC and positioned with respect to the post electrodes. Owing to this positioning of the stud bumps formed on the semiconductor IC with respect to the post electrodes, the planar position of the stud bumps is substantially fixed. As a result, it is possible to use a semiconductor IC having a very narrow electrode pitch of 100 ?m or smaller, particularly of around 60 ?m.

Abstract: A semiconductor-embedded substrate device according to the present invention can relax a thermal stress during fabrication or use and therefore has sufficient heat radiation properties and reliability. A semiconductor-embedded substrate (100) is a multilayer substrate obtained by stacking resin layers and has, inside of the resin layer (2), a semiconductor device (30) having a bump (32) connected to a terminal electrode (11) via an internal wiring (13) and connection plug (12). A heat radiation member (20) having an opening P in which one or more openings H have been formed is arranged immediately above and opposite to the back surface (30b) of the semiconductor device (30) and heat generated therein is transferred to and released from the heat radiation member (20).