Abstract: According to one embodiment, there is provided an integrated circuit. The integrated circuit includes a plurality of SRAMs including a first SRAM and a second SRAM, and a switching unit that enables switching between an electrically connected state where a first circuit portion on a source side of the first SRAM is electrically connected with a second circuit portion on a source side of the second SRAM and an electrically disconnected state where the first circuit portion is electrically disconnected from the second circuit portion.

Abstract: According to one embodiment, there is provided an integrated circuit. The integrated circuit includes a plurality of SRAMs including a first SRAM and a second SRAM, and a switching unit that enables switching between an electrically connected state where a first circuit portion on a source side of the first SRAM is electrically connected with a second circuit portion on a source side of the second SRAM and an electrically disconnected state where the first circuit portion is electrically disconnected from the second circuit portion.

Abstract: A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A control signal output circuit outputs a control signal based on the first potential. A pulse width adjustment circuit adjusts a pulse width of a word line voltage of the cell array based on the control signal. An amplitude of a voltage applied to bit lines connected to the memory cells is controlled with the pulse width.

Abstract: A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A control signal output circuit outputs a control signal based on the first potential. A pulse width adjustment circuit adjusts a pulse width of a word line voltage of the cell array based on the control signal. An amplitude of a voltage applied to bit lines connected to the memory cells is controlled with the pulse width.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including an SRAM cell; and a first voltage generator including first and second circuits. The first and second circuits include a diode-connected first transistor and a diode-connected second transistor, respectively. A driving capability of the first transistor is different from a driving capability of the second transistor. When the SRAM cell is in a standby state, the first voltage generator applies a second voltage or a third voltage to the SRAM cell via the first circuit or the second circuit.

Abstract: According to one embodiment, a semiconductor memory device includes a retention section that retains data by using a pair of first conductivity-type load transistors and a pair of second conductivity-type drive transistors, and a transfer section with transistors that operate to transfer data to and from the retention section and has a gate length shorter than the gate length of at least one of the drive transistors and the load transistors.

Abstract: According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock.

Abstract: According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock.

Abstract: A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

Abstract: A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

Abstract: A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

Abstract: According to the present invention, a turbine shell is manufactured by a method which includes the steps of preparing a planar blank, simultaneously forming a plurality of blade fixture slits 32A, 32B and 32C in the blank 40, and deforming the blank 40 into a curved concave shape by effecting drawing work.

Abstract: According to the present invention, a turbine shell is manufactured by a method which includes the steps of preparing a planar blank, simultaneously forming a plurality of blade fixture slits 32A, 32B and 32C in the blank 40, and deforming the blank 40 into a curved concave shape by effecting drawing work.

Abstract: According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer is formed on a compound semi-conductor substrate, and source/drain electrodes are formed on the active layer to be separated from each other. The wall insulating films are respectively formed on side walls of the electrodes, and a gate electrode is formed between the side wall insulating films to be respectively in contact therewith.

Abstract: An integrated circuit including a wafer having a GaAs substrate, an un-doped GaAs layer, and a GaAs active layer. This active layer may have an HEMT structure to improve its operation speed. Also, the substrate may a multi-layer structure to form a three dimensional capacitor. At least one mesa portion is formed on the substrate by removing a portion of the un-doped GaAs layer and GaAs active layer. A source electrode, for example, is formed on the mesa portion, and a ground electrode is formed on an exposed surface of the substrate. These electrodes are connected to each other by means of a wiring metal layer. As a result, the source electrode is easily grounded without using a long bonding wire.

Abstract: A mold for molding a semiconductor package including a semiconductor chip mounted on a lead frame, wherein a major surface of the semiconductor chip is inclined relative to a surface of the semiconductor package, the mold includes a first mold half including a first mold cavity having a first mold surface and at least four first side surfaces, a second mold half including a second mold cavity having a second main surface extending substantially parallel to the first main surface and at least four second side surfaces extending substantially perpendicular to the second main surface, and a portion for supporting the lead frame and the semiconductor chip in the first and second mold cavities and position the major surface of the semiconductor chip in an inclined position relative to the second main surface, wherein the portion for supporting and positioning includes a first mating surface on the first mold half inclined relative to the first main surface and a second mating surface on the second mold half inclin

Abstract: A semiconductor device for detecting or emitting a magnetic line of force or light is so provided that the major surface of its built-in semiconductor chip has a predetermined inclination angle relative to a mount surface of a mount substrate. An active layer of element for detecting a magnetic line of force or light or an element for emitting a magnetic line of force or light is formed on the major surface of the semiconductor chip. It is, therefore, possible to achieve a smaller mount thickness as defined relative to a mount surface and to detect a magnetic line of force or light coming in a direction parallel to the mount surface or to emit a magnetic line of force or light in a direction vertical to the mount surface.

Abstract: A chip including a Hall element for detecting a magnetic force is p repared. On the chip is formed an unhardened magnetic resin layer, which is formed of a mixture of soft magnetic powder an dsilicone rubber. The unhardened magnetic resin layer is applied with a magnetic field and is stretched in a direction perpendicular to one face of the chip, so that its top portion is formed in a substantially conical shape and its bottom portion is formed in a substantially rectangular block, the ratio of the length Wa of its base to its height Wb, Wb/Wa, being equal to or greater than 1. The magnetic resin layer is then hardened. As a result, a magnetic force detecting semiconductor device is provided, which has a magnetic resin layer with a high magnetic force convergence that has its top portion formed in a conical shape and its bottom portion formed in a rectangular block, the ratio of the length of its base to its height being equal to and greater than 1.

Abstract: A highly magnetic Hall element comprising a substrate, a Hall element chip mounted on the substrate, and a magnetic member interposed between the substrate and the chip. The magnetic member increases the coercive force of the element, and is formed by laminating resin layers mixed with powder having a high magnetic permeability, one upon another, by stencil printing on that side of a semiconductor wafer in which a Hall element is mounted. The wafer and the magnetic member are diced together, to provide a Hall element chip. The magnetic member formed on the Hall element chip is adhered to substrate, with half-cured surface put in contact with the substrate.

Abstract: Disclosed is a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate, and with its source/drain heavily doped regions, which are formed by doping Se in a lightly doped semiconductor layer on the GaAs substrate, self-aligned with both gate electrode and source/drain extraction electrodes.