Patents by Inventor Toshikazu HANAWA

Toshikazu HANAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11594489
    Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 28, 2023
    Assignee: Renesas Electronics Corporation
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya, Makoto Koshimizu
  • Patent number: 10872813
    Abstract: To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening for exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 22, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Mitsuhiro Sukegawa, Yoshinori Matsumuro, Toshikazu Hanawa, Kentaro Yamada
  • Publication number: 20200126853
    Abstract: To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening for exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Mitsuhiro SUKEGAWA, Yoshinori MATSUMURO, Toshikazu HANAWA, Kentaro YAMADA
  • Publication number: 20200066646
    Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Toshikazu HANAWA, Kazuhide FUKAYA, Makoto KOSHIMIZU
  • Patent number: 10224214
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: October 21, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Publication number: 20190043756
    Abstract: To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening f exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.
    Type: Application
    Filed: June 22, 2018
    Publication date: February 7, 2019
    Inventors: Mitsuhiro SUKEGAWA, Yoshinori MATSUMURO, Toshikazu HANAWA, Kentaro YAMADA
  • Patent number: 10043884
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshikazu Hanawa
  • Patent number: 9935023
    Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 3, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya, Kentaro Yamada
  • Publication number: 20180061769
    Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
    Type: Application
    Filed: June 30, 2017
    Publication date: March 1, 2018
    Inventors: Toshikazu HANAWA, Kazuhide FUKAYA, Makoto KOSHIMIZU
  • Publication number: 20180047579
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Application
    Filed: October 21, 2017
    Publication date: February 15, 2018
    Inventors: Kotaro HORIKOSHI, Toshikazu HANAWA, Masatoshi AKAISHI, Yuji KIKUCHI
  • Publication number: 20170338324
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Application
    Filed: August 8, 2017
    Publication date: November 23, 2017
    Inventor: Toshikazu HANAWA
  • Patent number: 9818620
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Publication number: 20170287722
    Abstract: The manufacturing yield of a semiconductor product is attempted to improve by reducing a particle and stabilizing an etching characteristic after the maintenance of a processing chamber in a dry etching equipment. The temperature in a processing chamber is raised to a temperature not lower than an actual process temperature after the maintenance of the processing chamber before the vacuation of the processing chamber, residual moisture adsorbing in the processing chamber is removed sufficiently, and successively the processing chamber is vacuated.
    Type: Application
    Filed: February 11, 2017
    Publication date: October 5, 2017
    Inventor: Toshikazu HANAWA
  • Publication number: 20170287794
    Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Toshikazu HANAWA, Kazuhide FUKAYA, Kentaro YAMADA
  • Patent number: 9761685
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshikazu Hanawa
  • Patent number: 9711423
    Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya, Kentaro Yamada
  • Patent number: 9666445
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 30, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Patent number: 9595468
    Abstract: To provide a semiconductor device having improved reliability. After formation of a first insulating film for an interlayer insulating film by spin coating, the surface of the first insulating film is subjected to a hydrophilicity improving treatment. A second insulating film for the interlayer insulating film is then formed on the first insulating film by spin coating. The interlayer insulating film is comprised of a stacked insulating film including the first insulating film and the second insulating film thereon. The interlayer insulating film therefore can have improved surface flatness.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: March 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya
  • Publication number: 20170062288
    Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
    Type: Application
    Filed: July 8, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Toshikazu HANAWA, Kazuhide FUKAYA, Kentaro YAMADA
  • Publication number: 20170053995
    Abstract: Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating film formed over a semiconductor substrate. At that time, a mask layer for formation of the opening is formed over the insulating film. The insulating film is dry etched and then wet etched. The dry etching step is finished before the semiconductor substrate is exposed at the bottom of the opening, and the wet etching step is finished after the semiconductor substrate is exposed at the bottom of the opening.
    Type: Application
    Filed: June 8, 2016
    Publication date: February 23, 2017
    Inventor: Toshikazu HANAWA