Patents by Inventor Toshikazu Hiraj

Toshikazu Hiraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7262470
    Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: August 28, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hiraj
  • Publication number: 20040222469
    Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.
    Type: Application
    Filed: February 6, 2004
    Publication date: November 11, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hiraj