Abstract: A display device includes gate lines, data lines, pixel electrodes, thin film transistors each of which is disposed near each of intersection portions of the data lines and the gate lines, a slope signal generator and a voltage adjuster. The slope signal generator that generates a slope signal to generate a falling waveform of a gate signal, the slope signal including a first voltage change period and a second voltage change period, the first voltage change period being sloped from a first voltage at which the thin film transistors are put into an on state to a second voltage lower than the first voltage, the second voltage change period being sloped from the second voltage to a third voltage at which the thin film transistors are put into an off state; and the voltage adjuster that adjusts the second voltage.

Abstract: A converter for connecting its ATM network with other ATM networks through a LAN, which is provided with an address translation table storing external VPIs, internal VPIs uniquely assigned to the LAN, and opposing MAC addresses for opposing converters in correspondence and a processing unit for performing control for transmitting, to the LAN, frames changed from the external VPI/VCIs of headers of cells from its ATM network to the internal VPI/VCIs by referring to the address translation table and having opposing MAC addresses corresponding to the internal VPI/VCIs attached, removing the opposing MAC addresses of frames received from the LAN by referring to the address translation table, and transmitting cells changed from internal VPI/VCIs to external VPI/VCIs to its ATM network.

Abstract: A converter for connecting its ATM network with other ATM networks through a LAN, which is provided with an address translation table storing external VPIs, internal VPIs uniquely assigned to the LAN, and opposing MAC addresses for opposing converters in correspondence and a processing unit for performing control for transmitting, to the LAN, frames changed from the external VPI/VCIs of headers of cells from its ATM network to the internal VPI/VCIs by referring to the address translation table and having opposing MAC addresses corresponding to the internal VPI/VCIs attached, removing the opposing MAC addresses of frames received from the LAN by referring to the address translation table, and transmitting cells changed from internal VPI/VCIs to external VPI/VCIs to its ATM network.

Abstract: A converter for connecting its ATM network with other ATM networks through a LAN, which is provided with an address translation table storing external VPIs, internal VPIs uniquely assigned to the LAN, and opposing MAC addresses for opposing converters in correspondence and a processing unit for performing control for transmitting, to the LAN, frames changed from the external VPI/VCIs of headers of cells from its ATM network to the internal VPI/VCIs by referring to the address translation table and having opposing MAC addresses corresponding to the internal VPI/VCIs attached, removing the opposing MAC addresses of frames received from the LAN by referring to the address translation table, and transmitting cells changed from internal VPI/VCIs to external VPI/VCIs to its ATM network.

Abstract: The fact is utilized that a threshold at which the degassing amount will steeply change upon variations in SiH content exists in the relation between the hydrophobic SiH content of an HSQ (Hydrogen SilsesQuioxane) film and the degassing amount from the HSQ film. An HSQ film having a relative SiH content or absolute H content so as to correspond to the threshold or more is used as one insulating layer in an insulating interlayer. The hygroscopicity of the HSQ film is reduced to suppress any line defects that are considered to be generated in an upper insulating layer owing to elimination of a hygroscopic component. Satisfied are both the demand for improving the reliability of a small contact hole and the demand for suppressing any interconnection delay. The integration degree of a semiconductor device can easily and reliably be increased.

Abstract: A monocrystalline layer of a III-V type or II-VI type compound semiconductor is epitaxially grown on a silicon substrate, and then subjected to a plurality of reheating steps during the cooling stage, wherein at least one of the upper limit temperatures of the reheating steps is lower than that used in the growing stage. The etch pit density is reduced to less than 10.sup.6 cm.sup.-2.

Abstract: A semiconductor device comprises a substrate of a first material, a buffer layer of a second, group III-V semiconductor material provided on the substrate epitaxially, and a barrier layer of a third, group III-V compound semiconductor material different from the first and second materials and having a resistivity substantially larger than the resistivity of the buffer layer. The barrier layer further has a second lattice constant different from the lattice constant of the buffer layer and characterized by a band gap substantially larger than the band gap of the buffer layer. The barrier layer is provided on the buffer layer directly and an active layer of a fourth, group III-V compound semiconductor layer is provided on the barrier layer. On the active layer, an active device is provided such that the active device at least has a part formed in the active layer.

Abstract: A semiconductor service having a group III-V compound semiconductor layer formed on a buffer structure for intercepting propagation of defects, in which the buffer structure comprises a first material layer of a group III-V compound semiconductor material, a second material layer of a group III-V compound semiconductor material provided on the first material layer, the second material layer containing a first group III element and a second group III element different from the first group III element with a graded compositional profile in which the content of the second group III element is decreased towards an upper boundary and a lower boundary of the second material layer.

Abstract: A semiconductor device comprises a substrate, a compound semiconductor layer provided on the substrate, and an active region formed on the compound semiconductor layer. The substrate in turn comprises a first semiconductor layer of a first semiconductor material, a second semiconductor layer of a second semiconductor material and provided on the first semiconductor layer, and a third semiconductor layer provided on the second semiconductor layer. The third semiconductor layer has a plurality of segments each defined by a pair of side walls that extend substantially perpendicular to the third semiconductor layer. The plurality of segments have a plurality of first-type segments and a plurality of second-type segments wherein the first- and second-type segments are arranged alternately when viewed in a direction parallel to the third semiconductor layer.

Abstract: A semiconductor device comprises a first semiconductor layer made of a single crystal of a first semiconductor material having a first lattice constant, a second semiconductor layer comprising a single crystal of a second semiconductor material having a second lattice constant which is different from the first lattice constant, a third semiconductor layer made of a third semiconductor material having a third lattice constant which is different from the first lattice constant, the third semiconductor layer being grown heteroepitaxially on the first semiconductor layer, a fourth semiconductor layer made of a fourth semiconductor material having a fourth lattice constant which is different from the third lattice constant, the fourth semiconductor layer being grown heteroepitaxially on the third semiconductor layer in a manner such that the second semiconductor layer is provided thereon, for preventing a first group of dislocations created in the third semiconductor layer from reaching the second semiconductor la