Patents by Inventor Toshikazu Ishikawa
Toshikazu Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9330942Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: GrantFiled: May 20, 2014Date of Patent: May 3, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshikazu Ishikawa, Mikako Okada
-
Patent number: 8975120Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: GrantFiled: March 11, 2014Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
-
Publication number: 20140252357Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshikazu ISHIKAWA, Mikako OKADA
-
Publication number: 20140193954Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
-
Patent number: 8766425Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: GrantFiled: November 15, 2013Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Toshikazu Ishikawa, Mikako Okada
-
Patent number: 8698299Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: GrantFiled: March 1, 2012Date of Patent: April 15, 2014Assignee: Renesas Electronics CorporationInventors: Toshikazu Ishikawa, Mikako Okada
-
Patent number: 8698296Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: GrantFiled: May 24, 2010Date of Patent: April 15, 2014Assignee: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
-
Publication number: 20140070214Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: ApplicationFiled: November 15, 2013Publication date: March 13, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshikazu ISHIKAWA, Mikako OKADA
-
Patent number: 8404497Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.Type: GrantFiled: November 15, 2010Date of Patent: March 26, 2013Assignee: Renesas Electronics CorporationInventors: Kazuya Maruyama, Toshikazu Ishikawa, Jun Matsuhashi, Takashi Kikuchi
-
Patent number: 8389339Abstract: It is aimed at improving the reliability of a semiconductor device. In a POP having an upper package stacked on a lower package, an opening of a first solder resist film in a first region between a first group of lands arranged at the periphery of an front surface of a wiring substrate of the lower package and a second group of lands arranged in a central part is filled with a second solder resist film, and thereby the formation of a starting point of cracks in the opening becomes unlikely to suppress occurrence of cracks and improve the reliability of the POP.Type: GrantFiled: September 16, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Yusuke Tanuma, Toshikazu Ishikawa
-
Patent number: 8383456Abstract: A multilayer wiring substrate has an upper surface with multiple bonding leads and a lower surface with multiple lands. Multiple wiring layers and insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper and lower surface sides of the core material. The third insulating layers are formed on the upper and lower surface sides of the core material with the second insulating layers in-between. The uppermost and lowermost wiring layers are formed over the third insulating layers.Type: GrantFiled: April 5, 2012Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventors: Mikako Okada, Toshikazu Ishikawa
-
Publication number: 20120208322Abstract: A multilayer wiring substrate has an upper surface with multiple bonding leads and a lower surface with multiple lands. Multiple wiring layers and insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper and lower surface sides of the core material. The third insulating layers are formed on the upper and lower surface sides of the core material with the second insulating layers in-between. The uppermost and lowermost wiring layers are formed over the third insulating layers.Type: ApplicationFiled: April 5, 2012Publication date: August 16, 2012Inventors: MIKAKO OKADA, Toshikazu Ishikawa
-
Patent number: 8222738Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: GrantFiled: August 18, 2011Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Yusuke Ota, Michiaki Sugiyama, Toshikazu Ishikawa, Mikako Okada
-
Publication number: 20120153282Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: ApplicationFiled: March 1, 2012Publication date: June 21, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshikazu ISHIKAWA, Mikako OKADA
-
Patent number: 8159058Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.Type: GrantFiled: September 4, 2008Date of Patent: April 17, 2012Assignee: Renesas Electronics CorporationInventors: Toshikazu Ishikawa, Mikako Okada
-
Patent number: 8159057Abstract: The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between.Type: GrantFiled: April 15, 2009Date of Patent: April 17, 2012Assignee: Renesas Electronics CorporationInventors: Mikako Okada, Toshikazu Ishikawa
-
Publication number: 20120083073Abstract: It is aimed at improving the reliability of a semiconductor device. In a POP having an upper package stacked on a lower package, an opening of a first solder resist film in a first region between a first group of lands arranged at the periphery of an front surface of a wiring substrate of the lower package and a second group of lands arranged in a central part is filled with a second solder resist film, and thereby the formation of a starting point of cracks in the opening becomes unlikely to suppress occurrence of cracks and improve the reliability of the POP.Type: ApplicationFiled: September 16, 2011Publication date: April 5, 2012Inventors: Yusuke TANUMA, Toshikazu Ishikawa
-
Patent number: 8138022Abstract: A first conductive member made of metal is provided over a first wiring substrate, which is a mounting substrate in the lower tier, a through hole is provided in a second wiring substrate, which is a mounting substrate in the upper tier, at a position corresponding to the first conductive member in a plan view, and a wiring is exposed at the sidewall of the through hole. The first conductive member is inserted into the through hole on the corresponding first wiring substrate side and the first wiring substrate and the second wiring substrate are electrically coupled by filling the through hole with a second conductive member. an electrode pad that is electrically coupled to the second conductive member and over which a semiconductor member in the upper tier is mounted is formed on the main surface side of the second wiring substrate.Type: GrantFiled: June 4, 2010Date of Patent: March 20, 2012Assignee: Renesas Electronics CorporationInventors: Michiaki Sugiyama, Takashi Miwa, Toshikazu Ishikawa, Tatsuya Hirai
-
Publication number: 20110300672Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: ApplicationFiled: August 18, 2011Publication date: December 8, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yusuke OTA, Michiaki SUGIYAMA, Toshikazu ISHIKAWA, Mikako OKADA
-
Patent number: 8021932Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: GrantFiled: April 27, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Yusuke Ota, Michiaki Sugiyama, Toshikazu Ishikawa, Mikako Okada