Patents by Inventor Toshikazu Kanaoka

Toshikazu Kanaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11331808
    Abstract: A robot for performing an expression by a non-verbal reaction, includes a body including a lower part provided so as to be capable of panning and tilting with respect to a support point coupled to a placement surface; a pair of arms provided to side parts of the body so as to be capable of moving up and down; and a head provided to an upper part of the body so as to be capable of panning and tilting, wherein the non-verbal reaction includes a combination of the tilting and the panning of the body with respect to the support point and movement of the pair of arms or the head or any combination thereof.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 17, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Masaru Ide, Shinji Kanda, Toshikazu Kanaoka, Kaoru Kinoshita
  • Patent number: 10885600
    Abstract: A communication control apparatus, including a memory, and a processor coupled to the memory and the processor configured to execute a process, the process including selecting one or more users from users based on intensities of received signals of sensor information transmitted by a plurality of tag devices associated with the users respectively, outputting information that instructs an operation for the plurality of tag devices, detecting the tag device for which the operation has been performed based on acceleration information of the plurality of tag devices, and causing a service provision device to output sound information regarding a service for a specific user associated with the detected tag device.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 5, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Masaru Ide, Shinji Kanda, Toshikazu Kanaoka, Kaoru Kinoshita
  • Publication number: 20200364444
    Abstract: A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a process, the process including: determining, when a distance from a sensor to a target person is equal to or greater than a threshold value, whether the target person satisfies a first criterion included in first reference information for each of the plurality of persons, the distance being detected by the sensor; capturing, when the distance is less than the threshold value, a first image of the target person by a camera provided in a vicinity of the sensor; and performing a face authentication process for the target person on the first image preferentially using second reference information corresponding to the first reference information including a second criterion determined to be satisfied by the target person.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: TOSHIKAZU KANAOKA, Norio NAGAHAMA, Yuki Yoshimura, Rieka Kouge
  • Publication number: 20200012847
    Abstract: An object detection apparatus includes: a camera configured to capture an image of an object; one or more of sensor devices each of which is configured to detect an environmental change; and a processor configured to (a): execute a determining process that includes, when any one of the one or more of sensor devices detects an environmental change, detecting a search starting point of the object based on at least one of a time corresponding to the detection and detection information from the sensor device, (b): execute an entry registering process that includes registering an entry with reference information when the object is detected, the entry including at least one of the time and the detection information and a direction in which the object is detected, wherein the determining process is configured to determine the direction toward which the camera is to be turned based on the reference information.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Applicant: Fujitsu Limited
    Inventors: Akihito Yoshii, Toshikazu Kanaoka, Toru Kamiwada
  • Publication number: 20190066253
    Abstract: A communication control apparatus, including a memory, and a processor coupled to the memory and the processor configured to execute a process, the process including selecting one or more users from users based on intensities of received signals of sensor information transmitted by a plurality of tag devices associated with the users respectively, outputting information that instructs an operation for the plurality of tag devices, detecting the tag device for which the operation has been performed based on acceleration information of the plurality of tag devices, and causing a service provision device to output sound information regarding a service for a specific user associated with the detected tag device.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: FUJITSU LIMITED
    Inventors: MASARU IDE, Shinji Kanda, TOSHIKAZU KANAOKA, Kaoru Kinoshita
  • Publication number: 20190054626
    Abstract: A robot for performing an expression by a non-verbal reaction, includes a body including a lower part provided so as to be capable of panning and tilting with respect to a support point coupled to a placement surface; a pair, of arms provided to side parts of the body so as to be capable of moving up and down; and a head provided to an upper part of the body so as to be capable of panning and tilting, wherein the non-verbal reaction includes a combination of the tilting and the panning of the body with respect to the support point and movement of the pair of arms or the head or any combination thereof.
    Type: Application
    Filed: October 24, 2018
    Publication date: February 21, 2019
    Applicant: FUJITSU LIMITED
    Inventors: MASARU IDE, Shinji Kanda, TOSHIKAZU KANAOKA, Kaoru Kinoshita
  • Patent number: 10109298
    Abstract: An information processing apparatus including: a memory, and a processor coupled to the memory and the processor configured to: detect a plurality of sounds in sound data captured in a space within a specified period, classify the plurality of sounds into a plurality of kinds of sound based on similarities of the plurality of sounds respectively, and determine a state of a person in the space within the specified period based on counts of the plurality of kinds of sound.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 23, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shigeyuki Odashima, Toshikazu Kanaoka, Katsushi Miura, Keiju Okabayashi
  • Publication number: 20170154639
    Abstract: An information processing apparatus including: a memory, and a processor coupled to the memory and the processor configured to: detect a plurality of sounds in sound data captured in a space within a specified period, classify the plurality of sounds into a plurality of kinds of sound based on similarities of the plurality of sounds respectively, and determine a state of a person in the space within the specified period based on counts of the plurality of kinds of sound.
    Type: Application
    Filed: November 28, 2016
    Publication date: June 1, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Shigeyuki Odashima, TOSHIKAZU KANAOKA, Katsushi Miura, Keiju Okabayashi
  • Patent number: 8151162
    Abstract: An error correction device error corrects without increasing in circuit scale. An encoder, includes: a first ECC encoder which interleaves a data string into n (n?2) blocks of data strings at every m (m?2) bits, and adds the error correction code parity; a parity encoder which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder, which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Kanaoka, Toshio Ito
  • Patent number: 8102615
    Abstract: A data storage apparatus includes: a medium for storing data having synchronization marks and data blocks, the synchronization mark and the data block being allocated alternately in the circumference direction of the medium; a head writing data into or reading out data from the medium; and a processor for executing a process including: reading out synchronization marks, measuring time for the head to pass through each of the data blocks based on signals read out from each of the synchronization marks in the circumference direction, generating write/read clock for each of the data blocks, which is continuously changing in speed, by calculating difference in time for the head to pass through the each one of the data blocks and its adjacent one of the blocks on the basis of the time measured, and writing data into or reading out data from the medium in synchronization with the write/read clock.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 24, 2012
    Assignee: Toshiba Storage Device Corporation
    Inventors: Akihiro Itakura, Toshikazu Kanaoka
  • Patent number: 8042030
    Abstract: An ECC decoder outputs, to a likelihood substituting unit, information on data in data blocks that is corrected to be valid. Based on the information, the likelihood substituting unit substitutes likelihood corresponding to the data corrected to be valid by the maximum value, and outputs it to an LDPC decoder. The LDPC decoder decodes user data with likelihoods partly substituted by the maximum value using LDPC parity, and calculates likelihood of data that constitutes the user data. The LDPC decoder outputs the calculated likelihood to a channel APP decoder as external data.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: October 18, 2011
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Kanaoka, Toshio Ito
  • Patent number: 8015499
    Abstract: A reproducing device performs decoding by propagating the reliability, and detects micro medium defects to correct the reliability information. The decoder has an internal decoder, external decoder and a defect detector which calculates a moving average value of a soft-input signal, acquires a scaling factor from this, and manipulates the reliability information of the internal decoder. Since micro-defects can be detected accurately and the reliability information of the internal decoder is manipulated, error propagation due to micro defects can be suppressed.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Limited
    Inventor: Toshikazu Kanaoka
  • Patent number: 8000050
    Abstract: A magnetic storage control apparatus for controlling a magnetic storage apparatus that uses a recording medium having a plurality of reference signals on its track and having a data area between the reference signals. The apparatus includes: a measurement section that reproduces the reference signal in a predetermined track of the recording medium and measures, for each data area, the time for a head to scan the data area to obtain a measurement value; a calculation section that calculates a setting value concerning the frequency of a recording clock used in data recording based on the measurement values of a plurality of data areas obtained by the measurement section; and a generation section that generates the recording clock based on the measurement values obtained by the measurement section and setting value calculated by the calculation section.
    Type: Grant
    Filed: March 28, 2009
    Date of Patent: August 16, 2011
    Assignee: Toshiba Storage Device Corporation
    Inventors: Toshikazu Kanaoka, Akihiro Itakura
  • Publication number: 20090307561
    Abstract: A decoding device includes a decoding unit that decodes an information data string including an error-correction parity for each interleaved data string obtained by interleaving the information data string for each symbol to generate a decoded data string; an error-correcting decoding unit that interleaves the decoded data string to perform error-correcting decoding, de-interleaves the interleaved decoded data strings after error-correcting decoding when all errors in the decoded data strings are corrected, and generates a decoded data string after error correction when errors are remained; and an event error-correcting unit that corrects data in the decoded data string for the merge section when an error-corrected portion in the decoded data string obtained by comparing the decoded data string and the decoded data string after error correction is in an event information string indicative of a merge section in the decoded data string.
    Type: Application
    Filed: March 30, 2009
    Publication date: December 10, 2009
    Applicant: Fujitsu Limited
    Inventor: Toshikazu KANAOKA
  • Patent number: 7620882
    Abstract: A decoder decodes a code by selecting, based on a predetermined condition, a path out of paths representing a transition of each of states in a trellis diagram. A storing unit stores, when a path at time k is selected, information on a selection history of a path selected at time prior to time (k?(a constraint length of a code)+1). A path detecting unit detects a path to be excluded from a path selection candidate, based on the information stored in the storing unit and information on a state of a transition source when a state transition occurs from time k?1 to time k.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 17, 2009
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Kanaoka, Toshihiko Morita
  • Patent number: 7620873
    Abstract: An information sequence having a code length of N (N=K+M), where K is information length and M is parity length, is encoded into a code sequence by using an LDPC code. The LDPC code is generated based on a matrix H, with M rows and N columns. The matrix H includes a check matrix H2 and a check matrix H1 . The check matrix H2 has M rows and M columns, it is a cyclic permutation matrix, and an inverse matrix exists for the check matrix H2, and its column weight is 3. The check matrix H1 has M rows and K columns.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: November 17, 2009
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Kanaoka, Toshihiko Morita
  • Publication number: 20090262404
    Abstract: In a hologram recording medium, a bleaching beam irradiated to fix recorded information is prevented from spreading and advancing into an unrecorded area. The hologram recording medium is provided with a hologram material layer for recording information to be recorded by irradiating a same area with an information beam which corresponds to the information to be recorded and a reference beam for reading out the recorded information. The hologram material layer is divided into a plurality of recording zones by a plurality of light blocking walls, and the light blocking walls are formed in the recording zone to which recording process has been performed, by using a material not passing through the bleaching beam irradiated for fixing the recorded information.
    Type: Application
    Filed: August 28, 2006
    Publication date: October 22, 2009
    Applicant: Fujitsu Limited
    Inventors: Akiyoshi Uchida, Toshikazu Kanaoka
  • Publication number: 20090244756
    Abstract: A data storage apparatus includes: a medium for storing data having synchronization marks and data blocks, the synchronization mark and the data block being allocated alternately in the circumference direction of the medium; a head writing data into or reading out data from the medium; and a processor for executing a process including: reading out synchronization marks, measuring time for the head to pass through each of the data blocks based on signals read out from each of the synchronization marks in the circumference direction, generating write/read clock for each of the data blocks, which is continuously changing in speed, by calculating difference in time for the head to pass through the each one of the data blocks and its adjacent one of the blocks on the basis of the time measured, and writing data into or reading out data from the medium in synchronization with the write/read clock.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Akihiro Itakura, Toshikazu Kanaoka
  • Publication number: 20090244760
    Abstract: A magnetic storage control apparatus for controlling a magnetic storage apparatus that uses a recording medium having a plurality of reference signals on its track and having a data area between the reference signals. The apparatus includes: a measurement section that reproduces the reference signal in a predetermined track of the recording medium and measures, for each data area, the time for a head to scan the data area to obtain a measurement value; a calculation section that calculates a setting value concerning the frequency of a recording clock used in data recording based on the measurement values of a plurality of data areas obtained by the measurement section; and a generation section that generates the recording clock based on the measurement values obtained by the measurement section and setting value calculated by the calculation section.
    Type: Application
    Filed: March 28, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Toshikazu KANAOKA, Akihiro Itakura
  • Publication number: 20090199073
    Abstract: An error correction device error corrects without increasing in circuit scale. An encoder, includes: a first ECC encoder which interleaves a data string into n (n?2) blocks of data strings at every m (m?2) bits, and adds the error correction code parity; a parity encoder which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder, which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated.
    Type: Application
    Filed: November 24, 2008
    Publication date: August 6, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Toshikazu Kanaoka, Toshio Ito