Patents by Inventor Toshikazu Masumoto

Toshikazu Masumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5825085
    Abstract: The present invention implements an armoring case of a power semiconductor device which can prevent cracks from occurring by inserting the terminal portion of an electrode plate in the inserting hole of the armoring case and then bending the same, misregistration from occurring between the fastening bolt inserting hole of the terminal portion and the screw portion of a terminal nut, and the like, and which can easily be assembled automatically. A terminal nut cover is previously molded. The terminal nut cover includes a first concave portion which can cover and support the terminal nut so as not to rotate when fastening a bolt, and a second concave portion into which the tip of the screw portion of the bolt can project. The electrode plate whose terminal portion is previously bent into a predetermined shape by a press machine or the like, and the terminal nut cover having the terminal nut inserted in and supported by the first concave portion are provided in a metal mold for the armoring case.
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: October 20, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshikazu Masumoto, Hisatoshi Arita
  • Patent number: 5792676
    Abstract: Disclosed herein are a method of fabricating a power semiconductor device having joiners that (205) vertically extend from outer sides of leads (203, 204) of a tie bar (201) of a power circuit lead frame (20) respectively, while joiners (308) vertically extend from outer sides of leads (303, 307) of a tie bar (301) of a control circuit lead frame (30) respectively to be opposed thereto. Forward end portions (205a) of the joiners (205) are joined to rear surfaces of forward end portions (308a) of the joiners (308) at a device center portion.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: August 11, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshikazu Masumoto, Shinobu Takahama
  • Patent number: 5646445
    Abstract: In order to maintain parasitic inductances of main electrodes at low levels also during operation of a semiconductor device, upright portions of main electrode plates serving as paths of main currents are sealed in a side wall portion of a resin case, whereby the main electrode plates are fixed to the case while being maintained in parallel with each other. Further, lower end portions are opposed in parallel with each other through a flat insulating spacer. Thus, parasitic inductances caused in the main electrode plates are suppressed. Further, the lower end portions are not fixed to a circuit board but electrically connected to a power transistor through wires. Therefore, no deformation of the main electrodes is brought by thermal deformation of the circuit board following heat generation of the transistor, whereby the parallelism of the main electrode plates is maintained also during the operation of the device.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: July 8, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshikazu Masumoto, Shinobu Takahama
  • Patent number: 4814901
    Abstract: A video cassette recorder for rental use having a timer means for counting the preset time, a back up power-supply such as battery and so on, and a start means for starting said timer means whereby the recorder makes only the normal reproducing operation impossible to perform till the re-start is performed after the lapse of the preset time from the timer start.
    Type: Grant
    Filed: November 4, 1986
    Date of Patent: March 21, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masami Onishi, Toshikazu Masumoto, Kazumi Murakami, Kiyoshi Yoshida