Abstract: There is disclosed a flip chip semiconductor integrated circuit, which comprises an internal cell, an I/O buffer as an interface between the internal cell and an external unit, a solder ball, a GND or power supply wire, and an I/O buffer unit arranged on a chip. In this case, the components except the I/O buffer unit are formed in a unit and arranged on the chip, and the I/O buffer unit includes a signal solder ball for transferring signals with the external unit, an I/O buffer having a signal terminal connected to the signal solder ball, a first I/O buffer GND wire connected to a GND terminal of the I/O buffer, and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer.

Abstract: In a semiconductor integrated circuit having a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each of which is delayed by a delay time of i×T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using n clock signals input from the first circuit via n signal wirings, for at least a part of the n signal wirings, the positions of the edges of two clock signals transmitted on the two adjacent signal wirings are separated, as seen on the time base, by more than T in the time.

Abstract: In a semiconductor integrated circuit having a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each of which is delayed by a delay time of i×T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using n clock signals input from the first circuit via n signal wirings, for at least a part of the n signal wirings, the positions of the edges of two clock signals transmitted on the two adjacent signal wirings are separated, as seen on the time base, by more than T in the time.

Abstract: There is disclosed a flip chip semiconductor integrated circuit, which comprises an internal cell, an I/O buffer as an interface between the internal cell and an external unit, a solder ball, a GND or power supply wire, and an I/O buffer unit arranged on a chip. In this case, the components except the I/O buffer unit are formed in a unit and arranged on the chip, and the I/O buffer unit includes a signal solder ball for transferring signals with the external unit, an I/O buffer having a signal terminal connected to the signal solder ball, a first I/O buffer GND wire connected to a GND terminal of the I/O buffer, and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer.