Abstract: A signal processor includes an AD converter that converts a periodic analog signal output from a detector in accordance with a position Q of a motor to a digital signal at a predetermined conversion period, a tracking circuit that calculates a position P of the motor at an arithmetic period on the basis of the digital signal that is converted and output at the conversion period by the AD converter, an operation state identifier that identifies an operation state of the motor on the basis of the position P of the motor calculated by the tracking circuit, and an arithmetic period determiner that changes the arithmetic period of the tracking circuit in accordance with the operation state of the motor identified by the operation state identifier such that the position P of the motor calculated by the tracking circuit follows the actual position Q of the motor.

Abstract: A register device is provided with a plurality of sub-register devices. The plurality of sub-register devices are grouped into three sub-register device groups, with a signal processing unit constituted of inverters and a capacitative element provided between adjacent sub-register device groups. A transfer signal output by a transfer signal generator is amplified at the signal processing units. This structure achieves an accurate and efficient transfer of data within the sub-register devices from write register units to read register units.

Abstract: A semiconductor memory having a function that set/reset information is directly written into each of the memory cells is disclosed. The semiconductor memory device of the present invention comprises word lines, bit lines, set/reset lines and switch circuits each of which is coupled to one of the set/reset lines for applying either a first potential or a second potential in response to a control signal. The semiconductor memory device further includes memory cells for storing data therein. Each of the memory cells has a first node coupled to one of the word lines, a second node coupled to one of the bit lines, a third node coupled to receive the first potential, and a forth node coupled to one of the set/reset lines.

Abstract: A highly stable sense amplifier circuit for a RAM and ROM includes a bias generating circuit capable of changing a bias voltage corresponding to voltage shifts of data lines, and an amplifying circuit having a transistor, the conducting state of which is controlled by the bias voltage for amplifying the voltage differences of the data lines. When the voltage of the data lines shifts due to manufacturing deviations, the bias voltage also shifts but operates so as to compensate shifts of the transistor in the amplifying circuit, so that the sense amplifier circuit can amplify the voltage differences of the data lines in a stable manner. The sense amplifier circuit can be formed with switches for cutting off through-currents, so that the sense amplifier circuit or even the memory on which the sense amplifier circuit is formed can operate with low power consumption.

Abstract: A semiconductor integrated circuit device includes a sense amplifier for amplifying the data stored in a memory cell, activated in accordance with a binary output enable signal fed to the integrated circuit device, in order to reduce the power consumption thereof. When the output enable signal is at a first level, in which the output of the integrated circuit device becomes in a floating state after a memory cell is selected to be read out, the sense amplifier is disabled to reduce the power consumption. The sense amplifier is disabled in response to a signal from a control circuit, which produces a logical output signal based on output enable signal and a control signal used to activate the sense amplifier only for the read operation. While the sense amplifier is temporarily disabled, the output of the sense amplifier is latched by a latch circuit, which is also controlled by the output enable signal, to guarantee an output enable access time.

Abstract: In a semiconductor integrated circuit device, a sense amplifier (30A) is capable of operating selectively with a first operating point (VR1) or with a second operating point (VR2) at the time of address change. A control circuit (80) detects the output data output at the preceding read cycle and causes the sense amplifier to operate with said first operating point in accordance with the output data of the preceding read cycle. A match detecting circuit (210) may be provided to generate a match signal or a mismatch signal depending on whether or not the input and output of a data input delay circuit (200) match each other. When the mismatch signal is generated, a transfer gate (220) is turned off and a latch circuit is made operative so that the write data of the preceding cycle is held on a write data line connected to the output of the transfer gate.

Abstract: A semiconductor integrated circuit device includes a sense amplifier for amplifying the data stored in a memory cell, activated in accordance with a binary output enable signal fed to the integrated circuit device, in order to reduce the power consumption thereof. When the output enable signal is at a first level, in which the output of the integrated circuit device becomes in a floating state after a memory cell is selected to be read out, the sense amplifier is disabled to reduce the power consumption. The sense amplifier is disabled in response to a signal from a control circuit, which produces a logical output signal based on output enable signal and a control signal used to activate the sense amplifier only for the read operation. While the sense amplifier is temporarily disabled, the output of the sense amplifier is latched by a latch circuit, which is also controlled by the output enable signal, to guarantee an output enable access time.

Abstract: In a semiconductor integrated circuit device, a sense amplifier (30A) is capable of operating selectively with a First operating point (VR1) or with a second operating point (VR2) at the time of address change. A control circuit (80) detects the output data output at the preceding read cycle and causes the sense amplifier to operate with said first operating point in accordance with the output data of the preceding read cycle. A match detecting circuit (210) may be provided to generate a match signal or a mismatch signal depending on whether or not the input and output of a data input delay circuit (200) match each other. When the mismatch signal is generated, a transfer gate (220) is turned off and a latch circuit is made operative so that the write data of the preceding cycle is held on a write data line connected to the output of the transfer gate.