Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

Abstract: A semiconductor integrated circuit device includes cells, each of the cells including a gate electrode, which is provided on the well, and first diffusion layers of a second conductivity type which are provided in the well such that the first diffusion layers sandwich the gate electrode, the first diffusion layers functioning as sources/drains. The device further includes sub-regions which are arranged in a non-occupied area of the logic circuit structure region, each of the sub-regions including a conductive layer, which is provided on the well and has the same pattern shape as the gate electrode, and second diffusion layers of the first conductivity type, which have the same pattern shape as the first diffusion layers and are disposed spaced apart to sandwich the conductive layer, the second diffusion layers being electrically connected to the well.

Abstract: A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Abstract: A semiconductor integrated circuit device includes connection members arranged on an entire chip, a first I/O cell which is arranged on the periphery of the chip and has a first end portion on the peripheral side of the chip and a second end portion on the center side of the chip, a second I/O cell which is arranged inside the first I/O cell and has a third end portion on the peripheral side of the chip and a fourth end portion on the center side of the chip, first terminals formed on the first end portion and connected to the connection members, second terminals formed on the second end portion and connected to an internal circuit of the chip, third terminals formed on the third end portion and connected to the internal circuit, and fourth terminals formed on the fourth end portion and connected to the connection members.

Abstract: A semiconductor device includes a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers. The plurality of circuits are designed using a common design core to which a plurality of wiring data are allocated.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-ntact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.