Abstract: A vibratory conveying apparatus (10) comprises a trough (20) for conveying articles from an upstream side to a downstream side, a vibrator (30) for vibrating the trough (20), and an attachment/detachment mechanism (40) for attaching and detaching the trough (20) and the vibrator (30). The attachment/detachment mechanism (40) has a trough-side attachment/detachment member (50), a vibrator-side attachment/detachment member (70), and a lever (65). The trough-side attachment/detachment member (50), which is secured to a trough bottom plate (21), has a protruding part (55) disposed on the upstream side and an eccentric cam (66) disposed on the downstream side. The vibrator-side attachment/detachment member (70), which is secured to the vibrator (30), has a protruding part (72) disposed on the upstream side and a bent part (73) disposed on the downstream side.

Abstract: A vibratory conveying apparatus (10) comprises a trough (20) for conveying articles from an upstream side to a downstream side, a vibrator (30) for vibrating the trough (20), and an attachment/detachment mechanism (40) for attaching and detaching the trough (20) and the vibrator (30). The attachment/detachment mechanism (40) has a trough-side attachment/detachment member (50), a vibrator-side attachment/detachment member (70), and a lever (65). The trough-side attachment/detachment member (50), which is secured to a trough bottom plate (21), has a protruding part (55) disposed on the upstream side and an eccentric cam (66) disposed on the downstream side. The vibrator-side attachment/detachment member (70), which is secured to the vibrator (30), has a protruding part (72) disposed on the upstream side and a bent part (73) disposed on the downstream side.

Abstract: A form-fill-seal machine is capable of reducing poor sealing caused by a packaged article catching in lateral seal portions. The form-fill-seal machine is provided with an upper tube, a lower tube disposed therebelow, a former, a lateral sealing mechanism below the lower tube, and opening and closing sliding members. A packaged article is dropped through the interiors of the upper tube and the lower tube. The former winds a sheet of a film F around the circumference of the lower tube to convert same into a tubular film. The lateral sealing mechanism laterally seals the tubular film. The opening and closing sliding members, which are disposed between the upper tube and the lower tube, shut off an upwardly oriented flow of gas from the interior of the lower tube when in a closed state.

Abstract: A form-fill-seal machine is capable of reducing poor sealing caused by a packaged article catching in lateral seal portions. The form-fill-seal machine is provided with an upper tube, a lower tube disposed therebelow, a former, a lateral sealing mechanism below the lower tube, and opening and closing sliding members. A packaged article is dropped through the interiors of the upper tube and the lower tube. The former winds a sheet of a film F around the circumference of the lower tube to convert same into a tubular film. The lateral sealing mechanism laterally seals the tubular film. The opening and closing sliding members, which are disposed between the upper tube and the lower tube, shut off an upwardly oriented flow of gas from the interior of the lower tube when in a closed state.

Abstract: In a state where a silicon base material (1) is used as an anode, a fine platinum member (2) is used as a cathode, and an electrolyte solution (4) is arranged between the anode and the cathode, anodic oxidation is performed in constant current mode under the conditions where porous formation mode and electrolytic polishing mode coexist. The platinum member (2) is fitted in the silicon base material (1) with silicon elution, and processes such as hole making, cutting, single-side pressing are performed. Since the silicon base material can be processed at a room temperature with small energy, the crystal quality of the processing surface is not deteriorated. Thus, efficient and highly accurate processing can be performed without using a mechanical method, which consumes much material in conventional processes such as cutting of solar cell silicon base material, and without using laser whose energy unit cost is high, and furthermore, without leaving a crystal damage on a processed surface.

Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: The present invention provides a solid state light-emissive display apparatus of high brightness and efficiency, high reliability, and of thin type, and method of manufacturing the same at low cost. Said apparatus has the luminous thin film made up by laminating or mixing crystal fine particle coated with insulator (5) of nm size and fluorescent fine particles (7) of nm size, and the lower electrode and the transparent upper electrode sandwiching said luminous thin film, wherein the electrons injected from said lower electrode are accelerated in the crystal fine particle coated with insulator layer (6) not being scattered by phonons to become high energy ballistic electrons, and form excitons (13) by colliding excitation of fluorescent fine particles. Since said fluorescent fine particles are of nm size, the exciton concentration is high, and luminescence intensity by extinction of excitons is also high.

Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only-Memory) cannot be configured as a high speed/large capacity memory.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Abstract: By i) forming a layered structure of an undoped single crystalline Si layer and single crystalline Si.sub.0.8 Ge.sub.0.2 mixed crystal layer on an n-Si(100) substrate, a second undoped single crystalline Si layer on it, and a p type hydrogenated amorphous Si.sub.1-B C.sub.B layer on it, iii) mounting an n-Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer on an n-Si(100) substrate and forming a layered structure of an undoped single crystalline Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer and Si.sub.0.8 Ge.sub.0.2 layer, an undoped single crystalline Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer, and a p-Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer sequentially on it or iv) mounting an n type single crystalline Si layer on an n-Si(100) substrate and forming a layered structure of an undoped single crystalline Si layer and Si.sub.0.8 Ge.sub.0.1 Sn.sub.0.1 layer, an undoped single crystalline Si layer, and a p type single crystalline Si layer sequentially on it, a semiconductor optical device is obtained.