Abstract: For each display line cycle, inputs to a pair of differential input terminals of a driving circuit are alternately switched in a cycle shorter than the display line cycle between a gradation voltage and a reference voltage. According to this, a chopping operation of switching polarities of offset appearing at the output of the driving circuit within one display line is performed for a plurality of times, and accordingly, a pixel of each display line maintains brightness information in which the chopping operation is already performed. As a result, although a frame cycle is lengthened, it is difficult to visually recognize a brightness difference caused by the offset.

Abstract: The touch panel controller is connected with a touch panel having a plurality of drive electrodes, a plurality of detection electrodes, and a plurality of capacitance components formed at intersections of the drive and detection electrodes. A two-edge detection mode is adopted for the touch panel controller, in which signals arising on each detection electrode in synchronization with rising and falling edges of a drive pulse output to the drive electrodes, and alternately changing in polarity are accumulated in the integration circuit in terms of absolute value components. The integration circuit switches the connection of the integration capacitance between an input and an output before the drive pulse edge changing. The touch panel controller contributes to the shortening of the time for touch detection by the touch panel and the increase of the accuracy of touch detection.

Abstract: For each display line cycle, inputs to a pair of differential input terminals of a driving circuit are alternately switched in a cycle shorter than the display line cycle between a gradation voltage and a reference voltage. According to this, a chopping operation of switching polarities of offset appearing at the output of the driving circuit within one display line is performed for a plurality of times, and accordingly, a pixel of each display line maintains brightness information in which the chopping operation is already performed. As a result, although a frame cycle is lengthened, it is difficult to visually recognize a brightness difference caused by the offset.

Abstract: The touch panel controller is connected with a touch panel having a plurality of drive electrodes, a plurality of detection electrodes, and a plurality of capacitance components formed at intersections of the drive and detection electrodes. A two-edge detection mode is adopted for the touch panel controller, in which signals arising on each detection electrode in synchronization with rising and falling edges of a drive pulse output to the drive electrodes, and alternately changing in polarity are accumulated in the integration circuit in terms of absolute value components. The integration circuit switches the connection of the integration capacitance between an input and an output before the drive pulse edge changing. The touch panel controller contributes to the shortening of the time for touch detection by the touch panel and the increase of the accuracy of touch detection.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: A semiconductor integrated circuit for driving a liquid crystal display, capable of improving the quality of an image displayed by preventing an imbalance between the outputs of a pair of amplifiers for positive voltage and negative voltage for AC driving of the liquid crystal panel and transmission of noise from one amplifier to the other amplifier is realized. A driver circuit that generates and outputs dive signals to be applied to signal lines of the liquid crystal panel includes decoder circuits, each of which selects a gray-scale voltage corresponding to image data. It also includes amplifiers for positive voltage which perform impedance conversion of positive voltages selected by the decoder circuits and amplifiers for negative voltage which perform impedance conversion of negative voltages selected by the decoder circuits.

Abstract: A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.

Abstract: A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: It is aimed at being capable of easily changing a power supply startup procedure and complying with various display devices. A power supply circuit is provided between an instruction register of a liquid crystal driver and a powersupply unit. The power supply unit is not directly supplied with a setting value registered to the instruction register from a microprocessor unit. The microprocessor unit writes setting values to the instruction register without need for the time axis. To turn on the power, the time is measured inside the power supply sequencer. Set values are sequentially input to the power supply unit. The instruction register should be also capable of registering an input timing.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: It is aimed at being capable of easily changing a power supply startup procedure and complying with various display devices. A power supply circuit is provided between an instruction register of a liquid crystal driver and a power supply unit. The power supply unit is not directly supplied with a setting value registered to the instruction register from a microprocessor unit. The microprocessor unit writes setting values to the instruction register without need for the time axis. To turn on the power, the time is measured inside the power supply sequencer. Set values are sequentially input to the power supply unit. The instruction register should be also capable of registering an input timing.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: A semiconductor integrated circuit for driving a liquid crystal display, capable of improving the quality of an image displayed by preventing an imbalance between the outputs of a pair of amplifiers for positive voltage and negative voltage for AC driving of the liquid crystal panel and transmission of noise from one amplifier to the other amplifier is realized. A driver circuit that generates and outputs dive signals to be applied to signal lines of the liquid crystal panel includes decoder circuits, each of which selects a gray-scale voltage corresponding to image data. It also includes amplifiers for positive voltage which perform impedance conversion of positive voltages selected by the decoder circuits and amplifiers for negative voltage which perform impedance conversion of negative voltages selected by the decoder circuits.

Abstract: A two-stage decode system is provided which uses a pre-stage decoder comprising a pre-stage first decoder which decodes a bit of arbitrary part of address signals and a pre-stage second decoder which decodes the remaining bits, level shifters which respectively shift the levels of outputs of the pre-stage decoder, and post-stage decoders which respectively decode the decode outputs of the respective decoders in the pre-stage decoder, which have been level-shifted by the level shifters.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.