Abstract: A first switch circuit is provided between a gradation voltage selection circuit and an output circuit. The output circuit includes a test switch that disconnects the gradation voltage selection circuit from the output circuit in a test mode; a test switch that connects, in the test mode, the gradation voltage selection circuit to a tester connection terminal TESR1; and a test switch that connects, in the test mode, the output circuit to a tester connection terminal TESR2. A second switch circuit is provided between a gradation voltage generation circuit and the gradation voltage selection circuit to disconnect, in the test mode, the gradation voltage generation circuit from the gradation voltage selection circuit.

Abstract: A display driver includes a gradation data register that stores gradation data having a bit width, and a gradation voltage signal generator that generates a gradation voltage signal that has voltage according to the gradation data stored in the gradation data register and outputs the generated gradation voltage signal, the display driver further including a test circuit that is provided between the gradation data register and the gradation voltage signal generator, the test circuit connecting at least a plurality of bit lines among bit lines provided between both of the circuits through a common node in a test mode, so as to perform failure detection based on a value of current that flows in the common node.

Abstract: A first switch circuit is provided between a gradation voltage selection circuit and an output circuit. The output circuit includes a test switch that disconnects the gradation voltage selection circuit from the output circuit in a test mode; a test switch that connects, in the test mode, the gradation voltage selection circuit to a tester connection terminal TESR1; and a test switch that connects, in the test mode, the output circuit to a tester connection terminal TESR2. A second switch circuit is provided between a gradation voltage generation circuit and the gradation voltage selection circuit to disconnect, in the test mode, the gradation voltage generation circuit from the gradation voltage selection circuit.

Abstract: In a semiconductor device, at least one operational amplifier drives a capacitive load in accordance with a control signal. A bias changing circuit receives the control signal to generate a bias changing signal in synchronization with the control signal dependent upon a width of the control signal. A bias circuit controls a bias current flowing through the operational amplifier in accordance with the bias changing signal.

Abstract: In an apparatus for driving data lines of a liquid crystal display panel, a plurality of voltage followers are provided, and a plurality of output pads are connected to the data lines. A plurality of first switches are connected between the voltage followers and the output pads, and a plurality of second switches are connected between the output pads. First and second charge neutralization pads are connected to a most-upstream one and a most-downstream one of the output pads. A third switch is connected between one, respectively, of the first and second charge neutralization pads and the most-upstream or most-downstream one of the output pads.

Abstract: In a semiconductor device, at least one operational amplifier drives a capacitive load in accordance with a control signal. A bias changing circuit receives the control signal to generate a bias changing signal in synchronization with the control signal dependent upon a width of the control signal. A bias circuit controls a bias current flowing through the operational amplifier in accordance with the bias changing signal.

Abstract: In an apparatus for driving data lines of a liquid crystal display panel, a plurality of voltage followers are provided, and a plurality of output pads are connected to the data lines. A plurality of first switches are connected between the voltage followers and the output pads, and a plurality of second switches are connected between the output pads. First and second charge neutralization pads are connected to a most-upstream one and a most-downstream one of the output pads. A third switch is connected between one, respectively, of the first and second charge neutralization pads and the most-upstream or most-downstream one of the output pads.

Abstract: Disclosed herewith is a shift register for shifting data in series in synchronism with a shift clock signal and is composed of a plurality of data-shift gages connected in cascade, each of which includes a shift-in terminal and a shift-out terminal, and each of which further includes a first transfer gate, a first data hold circuit, a second transfer gate and a second data hold circuit connected in this order between the shift-in and shift-out terminals. Further provided in each of the data-shift stages is a gate circuit, in particular a NOR gate, which responds to logic levels at selected ones of the respective circuit connection points and produces a pulse signal.