Patents by Inventor Toshikazu Tsutsui

Toshikazu Tsutsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030200056
    Abstract: A semiconductor device analysis system is provided. In a data analysis mechanism (2a) included in a data analyzing EWS, a failure generator (11) artificially generates failure shape data about the shape of a failure assumed to occur in an actual semiconductor device. An analysis database (9) stores therein failure shape recognized data provided from a failure shape recognizer (8) and the failure shape data provided from the failure generator (11). A data processor (10) performs a failure analysis process based on the failure shape recognized data and the failure shape data.
    Type: Application
    Filed: October 8, 2002
    Publication date: October 23, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Toshikazu Tsutsui
  • Publication number: 20030057988
    Abstract: A semiconductor device inspecting method is provided which can detect electric faults in an in-line inspection. The positive electrode of a variable DC power supply (2) is connected to the back or a peripheral portion of a semiconductor substrate (4) and the negative electrode of the variable DC power supply (2) is connected to a conductive cantilever (3). A scan is performed with a given forward bias voltage (e.g. 1.0 V) applied between the cantilever (3) and the semiconductor substrate (4) and with the cantilever (3) in contact with a target contact plug (9). The current flowing through the cantilever (3) is then monitored with an ammeter (1) to obtain a current characteristic of each contact plug, making it possible to detect conduction faults which cannot be detected by simply observing the configuration.
    Type: Application
    Filed: June 4, 2002
    Publication date: March 27, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hitoshi Maeda, Fumihito Ohta, Yukari Imai, Toshikazu Tsutsui
  • Patent number: 6060781
    Abstract: First interconnect lines each having an electric capacity given by C and second interconnect lines respectively adjacent thereto are formed on an upper surface of an insulating film. The first interconnect lines and the second interconnect lines are electrically isolated from a substrate and are electrically floating. The second interconnect lines are connected to a third interconnect line. As a result, the second interconnect lines and the third interconnect line which are electrically connected to each other as a whole have an electric capacity given by 12C. The first interconnect lines are irradiated with charged particles. The difference in the amount of secondary electrons emitted from the first interconnect lines depending on the magnitude of the electric capacity is detected as a potential contrast and used to evaluate whether or not there is contact between the first interconnect lines and the respectively associated second interconnect lines.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: May 9, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kouetsu Sawai, Toshikazu Tsutsui
  • Patent number: 6016278
    Abstract: A method comprises steps of: forming a FBM (step S1); generating a second failure map by compressing data of the FBM (step S2); recognizing a failure mode from the second failure map (step S3); selecting a specific failure mode (step S4); and analyzing the specific failure mode by using a part of the corresponding FBM (step S5). This makes a detail analysis possible while suppressing the number of processing data, and thereby achieves a failure analysis method and device improving accuracy and reliability in comparison result.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: January 18, 2000
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Masaaki Furuta
  • Patent number: 6009545
    Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of foreign material, a defect or the like at the surface of a semiconductor wafer by a defect inspecting apparatus is stored. Also stored is data of physical coordinates obtained based on fail bit data from a tester. Data indicating an additional failure region is produced by an additional failure region estimating apparatus based on the fail bit data, and is stored. Collation produces data of corrected physical position coordinates by adding the stored data of limitation by failure mode to the stored data of physical position coordinates, and collates the data of corrected physical position coordinates with stored data of defect position coordinates. Accordingly, accuracy in collation is improved, and failure can be analyzed even if caused not by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: December 28, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Tohru Koyama, Fumihito Ohta, Yasukazu Mukogawa, Masaaki Furuta, Yohji Mashiko
  • Patent number: 5905650
    Abstract: Failures detected by a tester are collated with defects detected by a defect checking device (Step S6). The collation is performed by retrieving defects coincident with each failure within a tolerance R0. Based on a mean value of displacements between the failures and the defects which are coincident with each other, coordinate values of the defects are corrected (Step S10). The coordinate values are corrected only when a collating ratio S that is a ratio of failures with which defects are coincident to whole failures exceeds a constant value S0 (Step S7). As a result, a coordinate value of a defect having high precision is obtained.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: May 18, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Masaaki Furuta
  • Patent number: 5844850
    Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of a foreign material, a defect and the like at a surface of a semiconductor wafer by a defect inspecting apparatus is stored in storage means. Data of physical position coordinates obtained based on fail bit data from a tester is stored in storage means. Data indicating an additional failure region is produced by additional failure region estimating means based on the fail bit data, and is stored in storage means. Collating means produces data of corrected physical position coordinates by adding the data of limitation by failure mode stored in storage means to the data of physical position coordinates stored in storage means, and collates the data of corrected physical position coordinates with data of defect position coordinates stored in storage means.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 1, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Tohru Koyama, Fumihito Ohta, Yasukazu Mukogawa, Masaaki Furuta, Yohji Mashiko