Abstract: A microprocessor with a built-in instruction ROM is described. Arbitrary data is set in advance in a data register of the microprocessor. The arbitrary data is given to a program counter by a register indirect jump instruction. The microprocessor has a normal reset function and an additional reset function allowing reset from a predetermined address. The additional reset function is used when the logic level of a control signal input terminal is at a predetermined level when the reset signal to the reset terminal is cleared. The arbitrary data is transferred to the program counter by register indirect jump instruction and set in the program counter. The program is re-executed with this data as an instruction start address.

Abstract: A microprocessor which, following a reset signal, permits execution beginning from an arbitrary address. The microprocessor is constituted in a manner such that arbitrary data is set in advance in a data register as an address. The address in the data register is given to a program counter by a register indirect jump instruction which does not originate in the instruction ROM. The microprocessor has a resetting function in addition to the normal resetting function. The normal resetting function includes re-executing a program from a predetermined address, such as a zero address. The normal resetting function occurs in the case where the logical level of a control signal input terminal is a predetermined level at a point of time when the reset signal to the reset terminal is cleared. When the control signal is at a different level, the arbitrary data set in the data register is transferred to the program counter by the register indirect jump instruction and is set in the program counter.

Abstract: An operation circuit for performing either fixed or floating point mathematical operations, having a mode control function for a multiplier including a multiplier, an arithmetic logic unit (ALU) and a signal generating circuit. A signal specifying the operating mode of the ALU, either a fixed point mode or a floating point mode is used by the signal generating circuit for generating either a fixed point multiplication signal or a floating point multiplication signal to control the multiplier, respectively.

Abstract: An adder circuit includes a Manchester-carry-chain circuit which propagates a carry signal for each block consisting of plural bits, and a carry-look-ahead circuit which selects said carry signal in response to a carry propagation signal being generated by a full adder, and when the carry signal is not generated in the two consecutive blocks, an output from the Manchester-carry-chain circuit is selected by the carry-look-ahead circuit, so that the carry signal being inputted to the low-order block of the two blocks can be propagated as the carry signal to be outputted from the high-order block.

Abstract: A logic circuit comprises a subtracter for receiving first and second binary data and outputting a difference between the first and second data, a decoder for outputting the output of the subtracter when the first data is greater than the second data and an inversion signal of the output from the subtracter when the second data is greater than the first data, and a shifter for outputting the output of the decoder without modification when the first data is greater than the second data and a shifted value of the output from the decoder when the second data is greater than the first data.