Patents by Inventor Toshiki Kizu
Toshiki Kizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10356320Abstract: According to an embodiment, in an information processing device, when there is no change in a first image received from an image sensor, reception of the next first image is awaited. When there is a change in the first image, a second image having a higher resolution than the first image is received from the image sensor and processing for the second image is performed.Type: GrantFiled: September 8, 2015Date of Patent: July 16, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Shirota, Tatsunori Kanai, Junichi Segawa, Toshiki Kizu, Akira Takeda
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Patent number: 9826538Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: GrantFiled: September 29, 2015Date of Patent: November 21, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Patent number: 9552307Abstract: According to an embodiment, an information processing apparatus includes a secure OS, a non-secure OS, and a monitor. The monitor is configured to switch between the OSs. The secure OS includes a memory protection setting controller, a processing determination controller, and a secure device access controller. The memory protection setting controller is configured to set a protection address in a memory for each certain processing. The processing determination controller is configured to receive an access type, a physical address of an access destination, and data to be written, acquire a list of processing, and determine a type of processing to be performed. The secure device access controller is configured to receive the access type, the physical address of an access destination, and data to be written, and access a peripheral identified by the physical address.Type: GrantFiled: September 10, 2014Date of Patent: January 24, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jun Kanai, Hiroshi Isozaki, Toshiki Kizu, Shunsuke Sasaki, Shintarou Sano
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Patent number: 9536113Abstract: According to an embodiment, an information processing apparatus includes a main processor, a secure operating system (OS) module, a non-secure OS module, a secure monitor memory setting module, a timer, and an address space controller. When receiving a notification of an interrupt from the timer, a secure monitor instructs the secure OS module to execute certain processing. The secure OS module is configured to execute certain processing instructed by the secure monitor and store data of a result of the processing in a first memory area.Type: GrantFiled: September 10, 2014Date of Patent: January 3, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Isozaki, Jun Kanai, Shintarou Sano, Shunsuke Sasaki, Toshiki Kizu
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Publication number: 20160378693Abstract: According to one embodiment, an information processing apparatus includes a processor and a memory. The processor operates in a first state and a second state. The memory includes a first region and a second region. A first program code is written in the second region. The first program code is executed when a call of the function provided by an operation system is invoked. A second program code is written in the first region. The processor executes the second program code to replace a first instruction included in the first program code with a second instruction. The second instruction is for switching the second state and the first state.Type: ApplicationFiled: October 30, 2015Publication date: December 29, 2016Inventors: Shunsuke Sasaki, Toshiki Kizu, Hiroshi Isozaki, Jun Kanai, Shintarou Sano, Ryuta Nara
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Publication number: 20160080652Abstract: According to an embodiment, in an information processing device, when there is no change in a first image received from an image sensor, reception of the next first image is awaited. When there is a change in the first image, a second image having a higher resolution than the first image is received from the image sensor and processing for the second image is performed.Type: ApplicationFiled: September 8, 2015Publication date: March 17, 2016Inventors: Yusuke Shirota, Tatsunori Kanai, Junichi Segawa, Toshiki Kizu, Akira Takeda
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Patent number: 9286242Abstract: According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.Type: GrantFiled: March 5, 2014Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shintarou Sano, Shunsuke Sasaki, Hiroshi Isozaki, Jun Kanai, Toshiki Kizu, Ryuta Nara
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Publication number: 20160021675Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: ApplicationFiled: September 29, 2015Publication date: January 21, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki KIZU, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Patent number: 9178687Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: GrantFiled: July 15, 2014Date of Patent: November 3, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Publication number: 20150089213Abstract: According to an embodiment, an information processing apparatus includes a main processor, a secure operating system (OS) module, a non-secure OS module, a secure monitor memory setting module, a timer, and an address space controller. When receiving a notification of an interrupt from the timer, a secure monitor instructs the secure OS module to execute certain processing. The secure OS module is configured to execute certain processing instructed by the secure monitor and store data of a result of the processing in a first memory area.Type: ApplicationFiled: September 10, 2014Publication date: March 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi ISOZAKI, Jun KANAI, Shintarou SANO, Shunsuke SASAKI, Toshiki KIZU
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Publication number: 20150089246Abstract: According to an embodiment, an information processing apparatus includes a secure OS, a non-secure OS, and a monitor. The monitor is configured to switch between the OSs. The secure OS includes a memory protection setting controller, a processing determination controller, and a secure device access controller. The memory protection setting controller is configured to set a protection address in a memory for each certain processing. The processing determination controller is configured to receive an access type, a physical address of an access destination, and data to be written, acquire a list of processing, and determine a type of processing to be performed. The secure device access controller is configured to receive the access type, the physical address of an access destination, and data to be written, and access a peripheral identified by the physical address.Type: ApplicationFiled: September 10, 2014Publication date: March 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Jun KANAI, Hiroshi ISOZAKI, Toshiki KIZU, Shunsuke SASAKI, Shintarou SANO
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Publication number: 20150082053Abstract: According to one embodiment, an information processing apparatus includes a processor, a main memory, and a memory controller. The memory controller executes an access restriction for each memory region. A first program decodes a protected program which was encrypted in a secure mode. The first program places the protected program which was decoded in a memory region. A second program executes the protected program in a secure mode. The processor places a code region and a protected data region in the protected program which was decoded in a memory region having an access restriction by using the first program. When an access to the protected data region is confirmed, the processor confirms by using the second program that the access is caused by a command from the code region placed by the first program, and then, executes the command.Type: ApplicationFiled: March 5, 2014Publication date: March 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shintarou Sano, Shunsuke Sasaki, Hiroshi Isozaki, Jun Kanai, Toshiki Kizu, Ryuta Nara
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Publication number: 20140328376Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: ApplicationFiled: July 15, 2014Publication date: November 6, 2014Inventors: Toshiki KIZU, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Patent number: 8804788Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: GrantFiled: February 25, 2013Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Patent number: 8792533Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: GrantFiled: February 25, 2013Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Patent number: 8406273Abstract: A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.Type: GrantFiled: July 10, 2009Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Kizu, Yoshimitsu Shimojo, Yoshinori Shigeta, Yasuro Shobatake
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Publication number: 20130019230Abstract: According to an embodiment, a program generating apparatus includes a cross-compiling unit, a processing time calculating unit, a source code converting unit, and a self-compiling unit. The cross-compiling unit generates sin instruction string for each basic block based on a source code and specifies instructions performing a memory access. The processing time calculating unit calculates a processing time of the instruction string for each basic block. The source code converting unit inserts a first code, which adds the processing time of the basic block to an accumulated processing time variable of an executed thread of the basic block, and a second code, which calculates the processing time for the specified memory access and adds the calculated processing time to the accumulated processing time variable, into the source code. The self-compiling unit generates a performance estimating program outputting the accumulated processing time variable of the thread executed.Type: ApplicationFiled: March 19, 2012Publication date: January 17, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Yu Nakanishi, Toshiki Kizu, Shunsuke Sasaki, Takahiro Tokuyoshi
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Patent number: 8214679Abstract: A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.Type: GrantFiled: November 2, 2009Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuji Ishikawa, Toshiki Kizu, Ryuichiro Ohyama
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Publication number: 20100299541Abstract: A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.Type: ApplicationFiled: November 2, 2009Publication date: November 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuji Ishikawa, Toshiki Kizu, Ryuichiro Ohyama
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Patent number: 7808950Abstract: A radio communication apparatus determines whether a reception signal is received normally. The apparatus measures strengths of the reception signal, assesses frequency channels using a result whether the reception signal is received normally and a strength of the reception signal, and decides that zero or more of the frequency channels as unusable channel in accordance with a result of an assessment of the frequency channels. The apparatus transmits a radio signal using one of the frequency channels sequentially without using the unusable channel.Type: GrantFiled: October 25, 2005Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Kizu, Yoshimitsu Shimojo