Patents by Inventor Toshiki Matsubara
Toshiki Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097441Abstract: A management system includes a plurality of resources configured to be electrically connected to an external power supply, and a management device configured to manage the resources. The management device includes a planning unit and a management unit. The planning unit is configured to determine a power balancing plan of each of the resources by using first information on a use schedule of each of the resources and second information indicating a magnitude of an environmental load in a process of generating electric power to be supplied by the external power supply. The management unit is configured to manage the resources to cause each of the resources to operate according to the power balancing plan or a modified power balancing plan in power balancing of the external power supply.Type: ApplicationFiled: August 3, 2023Publication date: March 21, 2024Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, CHUBU ELECTRIC POWER MIRAIZ CO., INC., CHUBU ELECTRIC POWER CO., INC.Inventors: Yusuke HORII, Eiko Megan UCHIDA, Masashi TANAKA, Masato EHARA, Sachio TOYORA, Tomoya TAKAHASHI, Akinori MORISHIMA, Takuji MATSUBARA, Tohru NAKAMURA, Ryou TAKAHASHI, Kenta ITO, Toshiki SUZUKI, Atsushi MIYASHITA, Takashi OCHIAI
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Patent number: 10566420Abstract: A semiconductor device of an embodiment includes an overvoltage protection diode in which an N-type semiconductor layer and a P-type semiconductor layer, formed on an insulating film in a voltage supporting region, are alternately disposed adjacently to each other. The overvoltage protection diode is disposed at a corner portion on the upper face of the insulating film, and extends from the corner portion to the center portion of the semiconductor substrate.Type: GrantFiled: September 30, 2016Date of Patent: February 18, 2020Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
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Patent number: 10424578Abstract: A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer. The concentration peak of the p-type impurities is disposed in a non-boundary region between a boundary region and a boundary region.Type: GrantFiled: September 13, 2016Date of Patent: September 24, 2019Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
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Patent number: 10366976Abstract: A semiconductor switch SW that includes a collector electrode C, an emitter electrode E and a gate electrode G, a Zener diode 5A configured to include one end electrically connected to the collector electrode C, the other end electrically connected to the gate electrode G, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, a Zener diode 5B configured to include one end electrically connected to the gate electrode G, the other end electrically connected to the emitter electrode E, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, are provided. The Zener diode 5A and the Zener diode 5B are configured so as not to allow the voltage of the gate electrode G to be increased to an on-threshold voltage of the semiconductor switch SW in the reverse bias application state.Type: GrantFiled: December 22, 2016Date of Patent: July 30, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
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Patent number: 10361184Abstract: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.Type: GrantFiled: September 30, 2016Date of Patent: July 23, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
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Publication number: 20190148354Abstract: A semiconductor switch SW that includes a collector electrode C, an emitter electrode E and a gate electrode G, a Zener diode 5A configured to include one end electrically connected to the collector electrode C, the other end electrically connected to the gate electrode G, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, a Zener diode 5B configured to include one end electrically connected to the gate electrode G, the other end electrically connected to the emitter electrode E, and n-type semiconductor layers and p-type semiconductor layers alternately arranged adjacent to each other, are provided. The Zener diode 5A and the Zener diode 5B are configured so as not to allow the voltage of the gate electrode G to be increased to an on-threshold voltage of the semiconductor switch SW in the reverse bias application state.Type: ApplicationFiled: December 22, 2016Publication date: May 16, 2019Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
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Patent number: 10199483Abstract: In a semiconductor device according to an embodiment, ends of conductor portions are electrically connected to an overvoltage protection diode so that depletion occurs in a diffusion layer in a portion near an insulating film in a reverse bias application state, and/or ends of conductor portions are electrically connected to the overvoltage protection diode so that depletion occurs in a peripheral semiconductor region in a portion near the insulating film in the reverse bias application state.Type: GrantFiled: May 26, 2016Date of Patent: February 5, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
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Publication number: 20180331178Abstract: A semiconductor device of an embodiment includes an overvoltage protection diode in which an N-type semiconductor layer and a P-type semiconductor layer, formed on an insulating film in a voltage supporting region, are alternately disposed adjacently to each other. The overvoltage protection diode is disposed at a corner portion on the upper face of the insulating film, and extends from the corner portion to the center portion of the semiconductor substrate.Type: ApplicationFiled: September 30, 2016Publication date: November 15, 2018Applicant: Shindengen Electric Manufacturing Co., Ltd.Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
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Publication number: 20180331092Abstract: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.Type: ApplicationFiled: September 30, 2016Publication date: November 15, 2018Applicant: Shindengen Electric Manufecturing Co., Ltd.Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
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Publication number: 20180294257Abstract: A semiconductor device of an embodiment includes a conductive semiconductor substrate, an insulating film formed on the semiconductor substrate, an overvoltage protection diode configured to be formed on the insulating film and to include an n-type semiconductor layer and a p-type semiconductor layer alternately arranged adjacent to each other, and an insulating film that covers the overvoltage protection diode. The concentration of the p-type impurities in the p-type semiconductor layer is lower than the concentration of the n-type impurities in the n-type semiconductor layer. The concentration peak of the p-type impurities is disposed in a non-boundary region between a boundary region and a boundary region.Type: ApplicationFiled: September 13, 2016Publication date: October 11, 2018Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
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Publication number: 20180204935Abstract: In a semiconductor device according to an embodiment, ends of conductor portions are electrically connected to an overvoltage protection diode so that depletion occurs in a diffusion layer in a portion near an insulating film in a reverse bias application state, and/or ends of conductor portions are electrically connected to the overvoltage protection diode so that depletion occurs in a peripheral semiconductor region in a portion near the insulating film in the reverse bias application state.Type: ApplicationFiled: May 26, 2016Publication date: July 19, 2018Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Ryohei KOTANI, Toshiki MATSUBARA, Nobutaka ISHIZUKA, Masato MIKAWA, Hiroshi OSHINO
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Patent number: 7588962Abstract: A method for manufacturing a semiconductor device that includes a housing, formed of a polyamide-series thermoplastic resin, and a semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The surface of the package is modified by UV-irradiation to have adhesive properties to polyamide. A plurality of connector terminals extend from the package and housing in parallel. A portion of the terminals is also sealed in the housing together with the package. Thus, the device is easily produced by insert molding and has excellent moisture resistance.Type: GrantFiled: September 4, 2008Date of Patent: September 15, 2009Assignee: Kabushiki Kaisha Tokai Rika Denki SeisakushoInventors: Masaya Tajima, Katsuya Kogiso, Mitsuo Watanabe, Toshiki Matsubara, Kenji Sato
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Publication number: 20090023253Abstract: A method for manufacturing a semiconductor device that includes a housing, formed of a polyamide-series thermoplastic resin, and a semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The surface of the package is modified by UV-irradiation to have adhesive properties to polyamide. A plurality of connector terminals extend from the package and housing in parallel. A portion of the terminals is also sealed in the housing together with the package. Thus, the device is easily produced by insert molding and has excellent moisture resistance.Type: ApplicationFiled: September 4, 2008Publication date: January 22, 2009Inventors: Masaya Tajima, Katsuya Kogiso, Mitsuo Watanabe, Toshiki Matsubara, Kenji Sato
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Patent number: 6635926Abstract: A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.Type: GrantFiled: July 20, 2001Date of Patent: October 21, 2003Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Nobuki Miyakoshi, Toshiki Matsubara, Hideyuki Nakamura
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Publication number: 20030052396Abstract: A semiconductor device includes a housing, which is formed of a polyamide-series thermoplastic resin, and semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The package has a modified face that is modified by UV-irradiation to have adhesive properties to polyamide. A plurality of connector terminals extend from the packages in parallel. A portion of the terminals is also sealed in the housing together with the package. Thus, the device is easily produced by insert molding and has excellent moisture resistance.Type: ApplicationFiled: September 18, 2002Publication date: March 20, 2003Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHOInventors: Masaya Tajima, Katsuya Kogiso, Mitsuo Watanabe, Toshiki Matsubara, Kenji Sato
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Publication number: 20020024056Abstract: A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.Type: ApplicationFiled: July 20, 2001Publication date: February 28, 2002Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Nobuki Miyakoshi, Toshiki Matsubara, Hideyuki Nakamura