Abstract: In a plating system, a plating consumption coefficient per unit number of substrates subjected to a treatment is calibrated once every predetermined time interval, and a replenishing amount in response to consumption of an additive associated with a plating treatment is computed by use of a formula defined as “the plating consumption coefficient×the number of substrates subjected to the plating treatment” and the replenishing amount of the additive is replenished. Accordingly, an amount of consumption of the additive coincides with the replenishing amount thereof. As a result, a concentration of the additive contained in a plating solution can be maintained at a constant concentration.

Abstract: A field effect transistor includes a lower gate electrode, upper gate electrode, first, second, and third barrier films, and source and drain. The lower gate electrode is formed from silicon on a silicon substrate via a gate insulating film. The upper gate electrode is formed from copper above the lower gate electrode. The first barrier film has a conductivity capable of supplying to the lower gate electrode a current enough to drive a channel portion, covers the lower surface of the upper gate electrode, and impedes diffusion of copper. The second barrier film has a lower end in contact with the first barrier film, covers the side surfaces of the upper gate electrode, and impedes diffusion of copper. The third barrier film has an end portion in contact with the second barrier film, covers the upper surface of the upper gate electrode, and impedes diffusion of copper. The source and drain are formed in the silicon substrate to sandwich a region under the lower gate electrode.

Abstract: A field effect transistor includes a lower gate electrode, upper gate electrode, first, second, and third barrier films, and source and drain. The lower gate electrode is formed from silicon on a silicon substrate via a gate insulating film. The upper gate electrode is formed from copper above the lower gate electrode. The first barrier film has a conductivity capable of supplying to the lower gate electrode a current enough to drive a channel portion, covers the lower surface of the upper gate electrode, and impedes diffusion of copper. The second barrier film has a lower end in contact with the first barrier film, covers the side surfaces of the upper gate electrode, and impedes diffusion of copper. The third barrier film has an end portion in contact with the second barrier film, covers the upper surface of the upper gate electrode, and impedes diffusion of copper. The source and drain are formed in the silicon substrate to sandwich a region under the lower gate electrode.

Abstract: The present invention provides a method of forming a titanium polycide gate electrode. The method comprises the step of: forming a gate insulation film a top surface of a semiconductor substrate; forming a polysilicon layer on the gate insulation film; forming a silicon-rich titanium silicide layer on the polysilicon layer by a sputtering process so that a compositional ratio of silicon to titanium of the silicon-rich titanium silicide layer exceeds 2, where preferably the compositional ratio of titanium to silicon is in the range of 1:2.3 to 1:2.5 and more preferably 1:2.

Abstract: A miniature contact is incorporated in a semiconductor device for transferring an electric signal between a conductive wiring and an impurity region, and a titanium silicide and a single crystal silicon region doped with an impurity forms an ohmic contact; in order to form the ohmic contact, a surface portion of the single crystal silicon region is made amorphous by using an ion-bombardment, thereafter, titanium is deposited on the amorphous silicon to have the thickness ranging between 3 nanometers and 10 nanometers, and the titanium layer is converted to a titanium silicide layer through an annealing at 400 degrees to 500 degrees in centigrade, thereby forming the low-resistive ohmic contact without changing the impurity profile of the single crystal silicon region.

Abstract: A method of fabricating a semiconductor device is provided, which makes it possible to form a TiSi2 polycide gate structure having a crack-free TiSi2 film and which eliminates the process to lower the resistivity of a TiSi2 film. The method comprises the steps of: (a) providing a semiconductor substrate having an active region formed by an isolation dielectric; (b) selectively forming a gate dielectric in the active region; (c) forming a polysilicon film on the gate dielectric; (d) forming a TiSi2 film on the polysilicon film while the substrate is kept at a temperature of approximately 750° C. or higher; and (e) patterning the polysilicon film and the TiSi2 film to form a gate electrode with a polycide structure. In the step (e), no phase transition of TiSi2 from amorphous or C-49 phase to the C-54 phase occurs. A barrier film may be additionally provided between the polysilicon and TiSi2 films. Preferably, the temperature of the substrate has a highest value of approximately 850° C.

Abstract: In the formation of the wiring as a gate electrode of a polycide structure or a polymetal structure using a high melting-point metal, sharp recesses 24 on the surface of a polycrystalline silicon film 6 in the area situated the concave portions 4 generated at the ends of a trench element-isolating insulator 3 are removed. Thereafter an amorphous high melting-point metal silicide film or an amorphous high melting-point metal film via a nitride film of a high melting-point metal is formed on the flattened silicon film. Then, the amorphous high melting-point metal film or the like is crystallized to form a crystallized high melting-point metal film or the like. The polycrystalline silicon film 6a and the high melting-point metal silicide film 8 or the like are patterned to form the gate electrode of an MOS transistor. According to the manufacturing method, the occurrence of cracks in the high melting-point metal film or the high melting-point metal silicide film on a silicon film can be suppressed.

Abstract: According to a semiconductor device manufacturing method, the surface of a silicon substrate is defined by an element isolation region, a gate oxide film and a polysilicon film are formed, and then a titanium nitride film is formed on the polysilicon film at a substrate temperature of 400° C. to 600° C. by collimate sputtering. A titanium silicide film is further formed on the titanium nitride film. A stacked film structure constituted by the titanium silicide film, titanium nitride film, and polysilicon film is patterned to form a gate electrode. After that, an LDD side wall is formed. Since the titanium nitride film is formed in this manner by collimate sputtering, a titanium nitride film, with which the breakdown voltage of the gate oxide film is not decreased and which has a high barrier performance, can be realized.

Abstract: Formation of metal thin films by collimate sputtering with high productivity and high bottom coverages. The bottom coverages by collimate sputtering are increased by using a target having a high sputtered-particle emission probability in the range of angles at which the collimator passage rate is high, without increasing the aspect ratio of the collimator, that is, without lowering the productivity.

Abstract: A collimated sputtering method that enables to improve the deposition rate per applied unit power and the bottom coverage is provided. This method contains a step of controlling a condition of a glow discharge in a chamber to increase a rate of a sputtered species that is contained in a specified angle range and that passes through a collimator. The rate of the sputtered species that can pas through the collimator is increased. Also, the rate of the passed species travelling parallel to the normal direction is increased. The sputtering surface of the target contains a crystal plane that is approximately perpendicular to a crystal axis having a shortest interatomic distance.

Abstract: A method of forming an interconnection within a high aspect ratio contact hole includes, forming a contact hole in an insulation film over a silicon substrate so that a diffusion layer, formed on a surface of the silicon substrate, is shown through the contact hole, removing spontaneous oxide film from a surface of the diffusion layer shown through the contact hole, heating at a temperature in the range of 350.degree. C. to 450.degree. C. the substrate to deposit a titanium film having a first thickness t1 by a collimated sputtering method, heating the substrate to deposit a titanium nitride film having a second thickness t2 by a collimated sputtering method, and heating the substrate to cause a titanium silicidation reaction at a boundary between the titanium film and the silicon diffusion layer thereby forming a titanium silicide film on the silicon diffusion layer at the bottom of the contact hole. Thereafter, a conductive film is formed which covers the titanium nitride film.

Abstract: A simulation apparatus for simulating and optimizing a configuration of a sputtering apparatus including a target surface temperature calculating unit for calculating a temperature of a target surface in consideration of cooling of the target, an atom initial velocity calculating unit for calculating an initial velocity of atoms within the target based on the calculated target surface temperature, an ion incidence rate calculating unit for calculating an incidence rate of the incident ions into the target to determine a position at which the incident ions collide against the target, an atom trajectory calculating unit for obtaining trajectories of atoms within the target based on each of calculation results and a sputtered atom ejection angle distribution unit for extracting sputtered atoms based on the calculation results to obtain ejection angle distribution.

Abstract: A configuration simulating method for a layer deposited on a silicon wafer comprising the steps of: (a) generating a string of modeling data, obtained by connecting coordinate points on a contour of a section, wherein the section is obtained by cutting a plane perpendicular to an open surface of a cylindrical contact hole, for modeling a configuration of said cylindrical contact hole formed within said silicon wafer; (b) extracting flux vectors, flowing into a predetermined one of said coordinate points on the string of modeling data, by analyzing a flux vector of particles to be deposited on said silicon wafer, wherein said particles are present in a gas phase; (c) deriving an intersection of the straight line extended from said coordinate point in the direction of said flux vector; (d) judging whether said flux vector becomes null due to a shadow effect related to said cylindrical contact hole; (e) moving from said predetermined one of said coordinate points to another of said coordinate points correspondin

Abstract: A magnetron sputtering electrode 2 is attached to a vacuum chamber 1 to make it retain a Ti target 4 via a back plate 3. A substrate 9 is loaded on a substrate holder 8 provided at a lower portion of the vacuum chamber 1. A collimation plate 6 is provided between the substrate 9 and the Ti target 4 to pass through only the sputtered particles advancing in the vertical direction, and, at its outside, shield plates 5, 7 are provided. The shield plate 5 at the target side is shaped in a wave form and thus its surface area is increased so that nitrogen can be adsorbed as much as possible.