Patents by Inventor Toshimasa Ishikawa

Toshimasa Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Master-slave clocked CMOS flip-flop with hysteresis
    Patent number: 5107137
    Abstract: In a master-slave type flip-flop circuit comprising a master output holding circuit of the master stage circuit, the threshold value of the input circuit of the slave stage circuit has a hysteresis characteristic in which the high level threshold value is set to a higher value than the threshold value of the master output holding circuit and the low level threshold value is set to a lower value than the threshold value of the master output holding circuit. Due to the feature, a phenomenon is prevented in which the output is once inverted and then again inverted in the metastable state.
    Type: Grant
    Filed: September 4, 1990
    Date of Patent: April 21, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Kinugasa, Munenobu Kida, Toshimasa Ishikawa