Abstract: A general purpose register circuit that stores and outputs desired data as required by a program stored in a storage device, has a memory cell which is connected to a word line and a bit line for writing and reading of the data; and a multiplexer circuit which is connected to the bit line at an input thereof and to a control line for transmitting an output selection signal and selectively outputs one of the value of the data read from the memory cell and input thereto via the bit line and a fixed value, according to the output selection signal input thereto.

Abstract: A general purpose register circuit that stores and outputs desired data as required by a program stored in a storage device, has a memory cell which is connected to a word line and a bit line for writing and reading of the data; and a multiplexer circuit which is connected to the bit line at an input thereof and to a control line for transmitting an output selection signal and selectively outputs one of the value of the data read from the memory cell and input thereto via the bit line and a fixed value, according to the output selection signal input thereto.

Abstract: A memory cell data output circuit includes a sense amplifier circuit having a first input terminal supplied with an output signal from memory cells, a second input terminal connected to dummy cells, and an output terminal, first switching element having a gate supplied with a control signal, for switching between the first input terminal and the ground potential, and second switching element having a gate supplied with an inverted signal of the control signal, for switching between the second input terminal and a power source potential, wherein the first and second switching elements respectively set the first and second input terminals to the ground potential and power source potential by turning on the switches in a preset period before the sense amplifier starts the sensing operation according to the control signals and turning off the switches after completion of the preset period.

Abstract: A memory cell array stores data in its row and column directions. A counter counts clock signal pulses, represents the counted value by using binary system, and outputs, as the column address, values occupying predetermined lower bit positions, while supplying values occupying predetermined upper and lower bit positions into an adder circuit. The adder circuit processes the values supplied, and outputs, as the row address, the values thus processed, so that the memory cell array is accessed diagonally.

Abstract: A D/A converter, which has two output terminals, produces an estimated analog voltage signal from one output terminal which is connected to a comparator. The comparator compares the estimated analog voltage signal with an input analog voltage signal fed from an analog voltage signal source, thereby to produce a signal which corresponds to the difference in the respective values of the two intput analog voltage signals. The estimated analog voltage signal is output from the other output terminal of the D/A converter, which is connected to a load. The D/A converter can produce the analog voltage signal at either output terminal thereof.

Abstract: The R-2R type D/A converter comprises an R-2R type D/A converter circuit provided with first and second series circuits each comprising a resistor and a switch. The first series circuit is connected between one end of a ladder resistor circuit and the ground. The second series circuit is connected between the other end of the ladder resistor circuit and the ground. The switches in the first and second series circuits are selectively turned on/off, so that an output signal may be supplied in either direction. First and second analog circuits are connected one to each terminal of the R-2R type D/A converter circuit. By turning on/off the switches of the first and second series circuits, a D/A converted output signal may be supplied selectively to the first or second analog circuit.