Abstract: The present invention relates to a semiconductor device and a process for producing the same. The principal surface of a semiconductor pellet is provided with a plurality of first bonding pad electrodes arranged in a first arrangement state and a plurality of second bonding pad electrodes which are provided with substantially the same electric circuit functions as those of the corresponding first bonding pad electrodes and which are arranged in a second arrangement state that is different from the first arrangement state. By virtue of the above-described means, it is possible to connect together pad electrodes and mating external terminals of a mounting substrate in the same way regardless of whether the pellet is mounted according to the face-up or face-down method.

Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.

Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.

Abstract: A nonvolatile memory device comprising a plurality of memory cells composed of insulated gate-type field effect semiconductor elements, terminals for applying a writing voltage and a reading voltage to said plurality of memory cells, wirings for connecting in common insulated gate-type field effect transistor elements of said plurality of memory cells, and resistance elements or MISFET's which are connected between the wirings and the terminals, wherein said resistance elements or MISFET's are composed of a polycrystalline silicon film or a single crystal silicon film formed on the field insulation film.

Abstract: Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

Abstract: A programmable read only memory consists of a plurality of FAMOS's having a control gate. Control gates of the plurality of FAMOS's arrayed along the same row are commonly connected to a word line, and drains of the plurality of FAMOS's arrayed along the same column are commonly connected to a bit line. Sources of the plurality of FAMOS's are commonly connected, and are connected to a ground point of the circuit via resistance means. Bit lines which are selected when the data is to be written are provided with a high voltage. Floating gates of the non-selected FAMOS's are coupled by parasitic capacity which exists between the floating gate and the drain. Therefore, when the voltage of the bit line is raised, the voltage of the floating gate is undesirably raised correspondingly. In this case, however, voltage drops across said resistance means owing to the writing current which flows through the selected FAMOS, and the potential of the commonly connected sources is raised by the drop in the voltage.

Abstract: The constant-current circuit consists of two MISFETs connected in series and a gate bias circuit for these MISFETs. The drain voltage of the first MISFET is maintained substantially constant by the source voltage of the second MISFET. The first MISFET does not sustain the channel length modulation, because its drain voltage is substantially constant. Consequently, a constant output current is obtained through the drain of the second MISFET.

Abstract: An instruction altering system to be used with a program control system including a storage device for storing instructions, wherein when the operation code of an instruction which is about to be executed coincides with the operation code of an instruction to be changed or altered, a multiplexer is switched by the coincidence output of a comparator circuit, and the operation code of a second stored instruction is gated instead to the storage device in place of the first mentioned operation code.

Abstract: An addressing system in an information processor for accessing to data regularly scattered in the whole memory region, comprising an index register, an adder, an address register, an instruction register, and a circuit which detects information of a portion of an operation part of the instruction register. When the detection output of the detecting circuit is specified information, information of an address part of the instruction register and information of the index register are added by the adder. The result is stored into the address register. After designating an address, the added information is shifted to the index register.

Abstract: An incrementer circuit, wherein a "1" is added to binary input information of n digits to provide binary output information, characterized in that output information of the lowest digit is produced as inverted input information by an inverter circuit, and that output information of each of the second-lowest to nth digits is produced by passing either input information of the particular digit or its inverted signal from an inverter circuit through a corresponding one of transfer gate transistor paths, which are controlled by the information of the digits lower than the particular digit.