Patents by Inventor Toshimasa Kuchii

Toshimasa Kuchii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11147460
    Abstract: The present invention predicts a timing when there may occur a change in the physical condition of a user. A body condition predicting device (10) includes: a collating section (112) configured to collate biological data acquired by a biosensor (30) with a biological data pattern representing drifting over time of the biological data, the biological data pattern being associated with either or both attribute data and environmental data; and a biological data drifting predicting section (113) configured to predict, based on a result of collation performed by the collating section, the drifting over time of the biological data that occurs after the biosensor (30) acquires the biological data.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihisa Adachi, Yasuhiro Harada, Toshimasa Kuchii, Hitoshi Nakamura, Kazuyuki Matsuoka
  • Publication number: 20190282177
    Abstract: The present invention predicts a timing when there may occur a change in the physical condition of a user. A body condition predicting device (10) includes: a collating section (112) configured to collate biological data acquired by a biosensor (30) with a biological data pattern representing drifting over time of the biological data, the biological data pattern being associated with either or both attribute data and environmental data; and a biological data drifting predicting section (113) configured to predict, based on a result of collation performed by the collating section, the drifting over time of the biological data that occurs after the biosensor (30) acquires the biological data.
    Type: Application
    Filed: April 18, 2017
    Publication date: September 19, 2019
    Inventors: YOSHIHISA ADACHI, YASUHIRO HARADA, TOSHIMASA KUCHII, HITOSHI NAKAMURA, KAZUYUKI MATSUOKA
  • Patent number: 8391585
    Abstract: A defect detecting device includes a pixel value correcting section, a block-division processing section, and a defective/non-defective determining section. The pixel value correcting section corrects a pixel value of an inspection-target image, on which detection of a defective area is to be carried out, in such a manner that the defective area of the inspection-target image is emphasized with respect to the other areas of the inspection-target image. The block-division processing section divides, into plural blocks, the inspection-target image with pixel values having been corrected, and obtains a block addition value or a block mean value. The defective/non-defective determining section determines whether or not the defective area is present by carrying out statistical processing to determine whether an outlier of the block addition value or an outlier of the block mean value is present or not.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: March 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshimasa Kuchii
  • Patent number: 7882467
    Abstract: Provided are an evaluation method and device of a test pattern which enable an appropriate evaluation in a reliability test with a simulation time reduced and high accuracy. It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of a transistor determined by a voltage between terminals of the transistor is a transistor state. The method comprises steps of: verifying operation of a semiconductor integrated circuit at a gate level or higher; acquiring an appearance cell state continuously appearing for a predetermined time or more in the operation verification; acquiring an appearance transistor state using the corresponding appearance cell state in the operation verification for each transistor; and calculating a test activity ratio of the transistor using the corresponding appearance transistor state for each transistor.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: February 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshimasa Kuchii
  • Patent number: 7783103
    Abstract: A defect detecting device includes: a block generating section dividing an inspection image in which a defective region will be detected into a plurality of blocks; an intra-block sum calculating section calculating an intra-block sum for each of the blocks generated by the block generating section, the intra-block sum being a sum of pixel data for pixels in that block; and a statistical processing section and a defect determining section determining whether there exists a defective region by determining through statistical processing whether the intra-block sums have an outlier. Accordingly, the device determines whether there is a defective region in a digital image quickly and using small circuitry.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: August 24, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshimasa Kuchii, Hideyuki Ichihara
  • Patent number: 7646892
    Abstract: An image inspecting apparatus invention includes an original image storing memory 21 for storing an image data output from an image sensor 11, a filtering processing section 22 for obtaining a shading component-removed data in which the shading component is removed from the output image data, a preliminary processing memory 23 for storing the shading component-removed data, a block dividing/adding section 24 for dividing the shading component-removed data into blocks with a size of n×m and adding the shading component-removed data within the divided blocks to obtain a block divided/added data, a secondary processing memory 25 for storing the block divided/added data, a statistics processing section 26 for calculating an average value, a maximum value and a minimum value for the block divided/added data, a quality determining section 27 for determining a quality with the calculated average value, maximum value and minimum value and a determination result storing memory 28 for storing information for the block
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: January 12, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Satou, Toshimasa Kuchii
  • Publication number: 20090094569
    Abstract: Provided are an evaluation method and device of a test pattern which enable an appropriate evaluation in a reliability test with a simulation time reduced and high accuracy. It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of a transistor determined by a voltage between terminals of the transistor is a transistor state. The method comprises steps of: verifying operation of a semiconductor integrated circuit at a gate level or higher; acquiring an appearance cell state continuously appearing for a predetermined time or more in the operation verification; acquiring an appearance transistor state using the corresponding appearance cell state in the operation verification for each transistor; and calculating a test activity ratio of the transistor using the corresponding appearance transistor state for each transistor.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 9, 2009
    Inventor: Toshimasa KUCHII
  • Publication number: 20080205747
    Abstract: A defect detecting device 1 includes a pixel value correcting section 16, a block-division processing section 17, and a defective/non-defective determining section 19. The pixel value correcting section 16 corrects a pixel value of an inspection-target image, on which detection of a defective area is to be carried out, in such a manner that the defective area of the inspection-target image is emphasized with respect to the other areas of the inspection-target image. The block-division processing section 17 divides, into plural blocks, the inspection-target image with pixel values having been corrected, and obtains a block addition value, which is a value obtained by adding pixel values of pixels present in a block, or a block mean value, which is a value obtained by dividing the block addition value by the number of pixels present in the block.
    Type: Application
    Filed: December 26, 2007
    Publication date: August 28, 2008
    Inventor: Toshimasa KUCHII
  • Publication number: 20070071304
    Abstract: A defect detecting device includes: a block generating section dividing an inspection image in which a defective region will be detected into a plurality of blocks; an intra-block sum calculating section calculating an intra-block sum for each of the blocks generated by the block generating section, the intra-block sum being a sum of pixel data for pixels in that block; and a statistical processing section and a defect determining section determining whether there exists a defective region by determining through statistical processing whether the intra-block sums have an outlier. Accordingly, the device determines whether there is a defective region in a digital image quickly and using small circuitry.
    Type: Application
    Filed: September 26, 2006
    Publication date: March 29, 2007
    Inventors: Toshimasa Kuchii, Hideyuki Ichihara
  • Publication number: 20060126136
    Abstract: An image inspecting apparatus invention includes an original image storing memory 21 for storing an image data output from an image sensor 11, a filtering processing section 22 for obtaining a shading component-removed data in which the shading component is removed from the output image data, a preliminary processing memory 23 for storing the shading component-removed data, a block dividing/adding section 24 for dividing the shading component-removed data into blocks with a size of n×m and adding the shading component-removed data within the divided blocks to obtain a block divided/added data, a secondary processing memory 25 for storing the block divided/added data, a statistics processing section 26 for calculating an average value, a maximum value and a minimum value for the block divided/added data, a quality determining section 27 for determining a quality with the calculated average value, maximum value and minimum value and a determination result storing memory 28 for storing information for the block
    Type: Application
    Filed: November 4, 2005
    Publication date: June 15, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Satou, Toshimasa Kuchii