Patents by Inventor Toshimasa Makino

Toshimasa Makino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile semiconductor memory device that can suppress effect of threshold voltage variation of memory cell transistor
    Patent number: 6870771
    Abstract: In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: March 22, 2005
    Assignees: Renesas Technology Corp., Mitsubishi Electric Engineering Company Limited
    Inventors: Mitsuhiro Tomoeda, Atsushi Ohba, Toshimasa Makino
  • Nonvolatile semiconductor memory device that can suppress effect of threshold voltage variation of memory cell transistor
    Publication number: 20030043629
    Abstract: In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.
    Type: Application
    Filed: July 24, 2002
    Publication date: March 6, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsuhiro Tomoeda, Atsushi Ohba, Toshimasa Makino