Abstract: A nonvolatile memory device has a memory cell having its gate connected to a word line, its source connected to a ground potential and its drain connected to a power supply voltage via a bit line and a dummy cell having its gate connected to the word line, its source connected to the source potential and its drain connected to the power supply voltage via a dummy bit line. The bit line and the dummy bit line are connected to reset and set terminals of a sense amplifier circuit comprising a flip-flop circuit and a latch type of sense amplifier. The conductance of the dummy cell is made smaller than that of the memory cell so that the speed at which the potential on the bit line is lowered depends on the state of injection of electrons into the memory cell as compared with the speed at which the potential on the dummy bit line at a time of reading data.

Abstract: A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

Abstract: A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.