Patents by Inventor Toshimasa Saika

Toshimasa Saika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for software update in manner based on processing properties of devices via maintenance network while allowing data transmission between devices on another network
    Patent number: 5859977
    Abstract: A computer system is so configured as to be divided into a control system which should have high reliability and high responsiveness and an information system which does not access the control system. They are connected via a transmission path (transmission path of control system and transmission path of information system). Centralized management of development and maintenance is performed from a software maintenance system. In development and maintenance of software, management according to the feature of each software such as processing contents of each software, demanded reliability, and version up frequency is performed from a maintenance system for exclusive use by using a transmission path of information system. Thereby, development and maintenance having high reliability and expandability is realized.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: January 12, 1999
    Assignees: Hitachi, Ltd., Hitachi Process Engineering, Inc.
    Inventors: Shuji Nishiyama, Hiroaki Nakanishi, Hideki Sato, Hiroshi Kobayashi, Shigeru Endo, Toshimasa Saika, Teruyasu Nakahashi, Hiroyuki Hori, Tomohito Ebina, Keiichi Sannomiya, Shimako Tanno
  • Information processing system having performance measurement capabilities
    Patent number: 5651112
    Abstract: An information processing system capable of performance measurement by the use of a small amount of mounted hardware. The information processing system having central processors installed therein comprises a control circuit, and a performance measurement validation register for specifying whether a performance measurement function is valid or invalid. In a case where the validity of the measurement function has been specified by the register, the control circuit operates one loop in a duplex configuration as a performance measurement facility. At this time, counter #1-counter #3 are used as counters for totalizing performance information. On the other hand, in a case where the invalidity of the measurement function has been specified, both loops in the duplex configuration are operated as the central processors. At this time, the counter #1-the counter #3 are used as timer counters for controlling buses.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: July 22, 1997
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Atsushi Matsuno, Masanori Naito, Hiroshi Kobayashi, Masanori Horie, Hideki Sato, Masayuki Tanji, Shigeaki Wada, Toshimasa Saika