Patents by Inventor Toshimasa Shimizu

Toshimasa Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11758302
    Abstract: An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 12, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Chiaki Takano, Toshimasa Shimizu, Yuki Takizawa, Mark Pude, Hirotaka Murakami, Kevin Fronczak
  • Publication number: 20230070410
    Abstract: An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Chiaki Takano, Toshimasa Shimizu, Yuki Takizawa, Mark Pude, Hirotaka Murakami, Kevin Fronczak
  • Publication number: 20220345656
    Abstract: An imaging device includes a controller and a generator. The controller controls an imaging unit on the basis of a command and data received from a host in accordance with an I2C/I3C communication protocol. The generator generates a second control signal indicating whether or not to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) on the basis of a first control signal received from the host via a first route different from the I2C/I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C/I3C communication protocol.
    Type: Application
    Filed: July 21, 2021
    Publication date: October 27, 2022
    Inventors: Chiaki Takano, Toshimasa Shimizu, Robert James Childs, Robert Justin Jarnot, John Steven Childs, Scott Rogerson, Cody Cziesler
  • Patent number: 11477368
    Abstract: An imaging device includes a controller and a generator. The controller controls an imaging unit on the basis of a command and data received from a host in accordance with an I2C/I3C communication protocol. The generator generates a second control signal indicating whether or not to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) on the basis of a first control signal received from the host via a first route different from the I2C/I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C/I3C communication protocol.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: October 18, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Chiaki Takano, Toshimasa Shimizu, Robert James Childs, Robert Justin Jarnot, John Steven Childs, Scott Rogerson, Cody Cziesler
  • Patent number: 11400817
    Abstract: A controller of an embodiment includes a limiter receiving an active current command initial value, limiting a maximum value of the active current command initial value with a predetermined value, and outputting a first value; a circuit to calculate a reactive current command initial value; a calculator to calculate a reactive current command adjustment value; a unit receiving the first value as an input, and calculating a reactive current upper limit value such that a composite value of the first value and the reactive current upper limit value is equal to or smaller than an input current maximum value; and a limiter to output the reactive current command adjustment value or the reactive current upper limit value, whichever is smaller. The predetermined value is a value to set the reactive current upper limit value to a value larger than zero and smaller than the input current maximum value.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: August 2, 2022
    Assignees: Central Japan Railway Company, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Ken Kunomura, Toshimasa Shimizu, Kenji Sato, Hirokazu Kato, Kazuaki Yuuki, Toshiyuki Uchida, Masatsugu Morita, Hiroki Miyajima, Yukitaka Monden
  • Patent number: 11381192
    Abstract: Provided is a power conversion controller in which variation in reactive power among power conversion controllers can be inhibited while maintaining the running performance of vehicles. The power conversion controller includes a power factor setter that sets a power factor based on a detection value of an overhead line voltage, and a calculator that calculates a reactive current command value by multiplying an active current command value by a tangent of a power factor angle of the power factor. The power factor setter sets a reference value set in advance as the power factor if the detection value is within a reference range, sets a value smaller than the reference value as the power factor if the detection value is below the reference range, and sets a value larger than the reference value as the power factor if the detection value is beyond the reference range.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: CENTRAL JAPAN RAILWAY COMPANY
    Inventors: Ken Kunomura, Toshimasa Shimizu, Kenji Sato, Toshiaki Takami
  • Publication number: 20210367544
    Abstract: Provided is a power conversion controller in which variation in reactive power among power conversion controllers can be inhibited while maintaining the running performance of vehicles. The power conversion controller includes a power factor setter that sets a power factor based on a detection value of an overhead line voltage, and a calculator that calculates a reactive current command value by multiplying an active current command value by a tangent of a power factor angle of the power factor. The power factor setter sets a reference value set in advance as the power factor if the detection value is within a reference range, sets a value smaller than the reference value as the power factor if the detection value is below the reference range, and sets a value larger than the reference value as the power factor if the detection value is beyond the reference range.
    Type: Application
    Filed: October 30, 2020
    Publication date: November 25, 2021
    Inventors: Ken Kunomura, Toshimasa Shimizu, Kenji Sato, Toshiaki Takami
  • Patent number: 11150685
    Abstract: It is desirable to reduce power consumption without reducing a function in an electronic apparatus operating in a plurality of modes different in power consumption from one another. A processor operates in a normal mode, in which power consumption is higher, of two modes different in power consumption from each other, and stops operation in a power saving mode, in which the power consumption is lower, of the two modes. A control section outputs a power saving mode control command instructing an increase or decrease of a supply electric power to a digital circuit different from the processor in the power saving mode. A power source managing integrated circuit increases or decreases the supply electric power to the digital circuit in accordance with the power saving mode control command, and outputs the increased or decreased supply electric power.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 19, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keita Izumi, Toshimasa Shimizu, Katsumi Takaoka
  • Publication number: 20200238835
    Abstract: A controller of an embodiment includes a limiter receiving an active current command initial value, limiting a maximum value of the active current command initial value with a predetermined value, and outputting a first value; a circuit to calculate a reactive current command initial value; a calculator to calculate a reactive current command adjustment value; a unit receiving the first value as an input, and calculating a reactive current upper limit value such that a composite value of the first value and the reactive current upper limit value is equal to or smaller than an input current maximum value; and a limiter to output the reactive current command adjustment value or the reactive current upper limit value, whichever is smaller. The predetermined value is a value to set the reactive current upper limit value to a value larger than zero and smaller than the input current maximum value.
    Type: Application
    Filed: January 27, 2020
    Publication date: July 30, 2020
    Applicants: Central Japan Railway Company, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Ken KUNOMURA, Toshimasa SHIMIZU, Kenji SATO, Hirokazu KATO, Kazuaki YUUKI, Toshiyuki UCHIDA, Masatsugu MORITA, Hiroki MIYAJIMA, Yukitaka MONDEN
  • Patent number: 10591953
    Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 17, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Sotaro Ohara, Katsuyuki Tanaka, Katsumi Takaoka, Keita Izumi, Suguru Houchi, Gaku Hidai, Yutaka Takagi, Hideki Takahashi, Hideki Awata, Yasushi Katayama, Naoki Yoshimochi, Toshimasa Shimizu
  • Publication number: 20190235565
    Abstract: It is desirable to reduce power consumption without reducing a function in an electronic apparatus operating in a plurality of modes different in power consumption from one another. A processor operates in a normal mode, in which power consumption is higher, of two modes different in power consumption from each other, and stops operation in a power saving mode, in which the power consumption is lower, of the two modes. A control section outputs a power saving mode control command instructing an increase or decrease of a supply electric power to a digital circuit different from the processor in the power saving mode. A power source managing integrated circuit increases or decreases the supply electric power to the digital circuit in accordance with the power saving mode control command, and outputs the increased or decreased supply electric power.
    Type: Application
    Filed: November 7, 2017
    Publication date: August 1, 2019
    Inventors: Keita Izumi, Toshimasa Shimizu, Katsumi Takaoka
  • Publication number: 20180210487
    Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Inventors: SOTARO OHARA, KATSUYUKI TANAKA, KATSUMI TAKAOKA, KEITA IZUMI, SUGURU HOUCHI, GAKU HIDAI, YUTAKA TAKAGI, HIDEKI TAKAHASHI, HIDEKI AWATA, YASUSHI KATAYAMA, NAOKI YOSHIMOCHI, TOSHIMASA SHIMIZU
  • Patent number: 4209559
    Abstract: Novel polyester filamentary yarn is provided having (a) a fineness of 0.9 denier per filament or less, (b) an amorphous orientation in the range of 30% to 70% and (c) a negative .epsilon..sub.0.2 where said .epsilon..sub.0.2 is a structural integrity parameter. The yarn possesses ameliorated properties regarding a heat-setting property, a raising property, a dimensional stability and a twist resistance. The yarn finds its wide range of usage, for example, silky fabrics with an excellent fullness, pliability and liveliness, raised fabrics with thermally stabilized fluffs protruding straight-forwardly and an extremely soft hand, and uniformly creped fabrics with an improved surface contour are obtained therefrom.
    Type: Grant
    Filed: March 26, 1979
    Date of Patent: June 24, 1980
    Assignee: Teijin Limited
    Inventors: Osamu Wada, Yoshiyuki Sasaki, Shiro Kumakawa, Akio Kimura, Toshimasa Shimizu, Hiroyuki Nagai, Shunichi Takeda, Takumi Shimazu