Abstract: Provided is an object detecting device that does not require an operator to perform a complicated operation onsite and that allows the number of components to be reduced while a detection range can be set. Provided are: at least two sensor units configured to receive detection rays from different detection areas, the different detection areas being arranged in an up-down direction and having center lines extending in different diagonally downward directions; and an object detection determination section configured to detect an object in a detection range based on one or more of at least two detection signals corresponding to amounts of detection rays received by the at least two sensor units, respectively, the detection range being determined by setting a reference for the at least two detection signals.

Abstract: An oscillator includes a package having a first side, a second side, a third side, and a fourth side, a resonator and an oscillation circuit disposed in the package, an output terminal arranged along the first side of the package, and outputting a clock signal generated by the oscillation circuit, and a control terminal arranged along the second side of the package, and supplied with a digital control signal adapted to update an operation state of the oscillation circuit.

Abstract: An oscillator includes a package having a first side, a second side, a third side, and a fourth side, a resonator and an oscillation circuit disposed in the package, an output terminal arranged along the first side of the package, and outputting a clock signal generated by the oscillation circuit, and a control terminal arranged along the second side of the package, and supplied with a digital control signal adapted to update an operation state of the oscillation circuit.

Abstract: A differential signal output circuit is equipped with a first output stage including serially connected transistors QP1 and QN1, a second output stage including serially connected transistors QP2 and QN2, an input device 11-13 that supplies two signals having mutually reversed phases to the gate of the first output stage and the gate of the second output stage, respectively, based on an input signal, and a current supply device QP3 that supplies specified drain current to the first and second output stages.

Abstract: A clock generating circuit 10, for generating a clock signal of which frequency is variable, has a delay circuit 20, a selector 30 and a control circuit 40. The delay circuit 20 has buffers 21 to 24 for delaying the input clock signal and output terminals 30A to 30D each of which outputs a clock signal delayed by a different delay time. The selector 30 selects one of the output terminals in the delay circuit 20, based on the output from the control circuit 40. The control circuit 40 supplies an output signal formed of a group of bits that is circulated in a predetermined cycle, to the selector 30. A cycle in an output clock signals OUT sequentially outputted from the output terminal 12 through the output terminals selected by the selector 30 increases or decreases in accordance with the group of bits in the output signal. Thus, the frequency in the output clock signal OUT will vary to reduce EMI noise.

Abstract: A differential signal output circuit is equipped with a first output stage including serially connected transistors QP1 and QN1, a second output stage including serially connected transistors QP2 and QN2, an input device 11-13 that supplies two signals having mutually reversed phases to the gate of the first output stage and the gate of the second output stage, respectively, based on an input signal, and a current supply device QP3 that supplies specified drain current to the first and second output stages.

Abstract: A clock generation circuit that generates multi-phase output clock signals which immediately follow any change in the period of an input clock signal. This clock generation circuit comprises a voltage-controlled oscillator (14) that generates an output signal having a frequency that varies in response to a control voltage; a phase comparator (11) that compares the phase of the input clock signal and the phase of the output signal of the voltage-controlled oscillator, to detect the phase difference therebetween; control voltage generation circuits (12, 13) that generate a control voltage corresponding to that phase difference; and a variable delay circuit (15) that generates multi-phase output clock signals by delaying the input clock signal in accordance with the control voltage.

Abstract: A method of minimizing line capacitance for transmission lines in integrated circuits is presented to decrease the device performance problems of time delay and noise generation caused by capacitive coupling effects. The prime objective is to decrease the high line capacitance associated with such long length lines as clock lines, buslines and analogue signal lines as well as designated lines requiring low line capacitance. A procedure for applying CAD to such a design concept is also indicated. Although the present embodiments refer to transmission lines within one layer of an IC, the basic concept outlined is applicable also to multilayer designs.

Abstract: A resin sealed semiconductor integrated circuit device has an upper wiring layer crossing over a lower wiring layer via an intermediate insulating film. Recesses or protrusions are formed at the side face of the upper wiring layer in the vicinity of its intersecting boundary with the lower wiring layer.

Abstract: In a RST flip-flop circuit constructed with CMOS transistors, two transistors connected in parallel having an input signal (R,S) and a synchronizing signal (T) as the inputs are connected in series a transistor of the same conductivity type, for each of the set side and the reset side. The last mentioned transistor receives the output siganl from the opposite side, and the output signal on this side is taken out from the drain of this transistor.

Abstract: A gate-array device has a plurality of basic cell lines in the central portion of a semiconductor chip and a plurality of I/O cells at its peripheral portion, the basic cell lines being composed of a plurality of basic cells in which at least one P-channel MOS FET and at least one N-channel MOS FET are disposed in a direction perpendicular to the basic cell lines. In each of the basic cell lines, a predetermined number of P-channel MOS FET's and the predetermined number of N-channel MOS FET's are alternatively disposed in a direction in parallel to the basic cell lines.