Abstract: On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

Abstract: On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

Abstract: According to the present invention, the main word lines arranged in a row direction have a linear pattern shape, and in the region where sub word decoder circuits are formed, the pattern of the main word lines has a shape whereby the pattern branches and splits into a plurality of lines and then reconverges, in the direction of the row. In the region where the line splits, relatively small island-shaped patterns of the conducting layer are located, forming nodes which have a difference electric potential from the main word lines. The main word lines are constituted by a first metal conducting layer, similarly to the prior art. In other words, small island-shaped metal layer patterns, which are electrically different from the main word lines are formed inside the conducting metal layer pattern constituting the main word lines, similarly to island formed in the middle of a river, for example.

Abstract: A photomask has a plurality of transparent regions defined in an opaque region and classified into first and second groups. Each of the transparent regions belonging to one of the first and second groups is provided with a phase shifter, so that the phase of light transmitted through the transparent region belonging to the first group becomes different from the phase of light transmitted through the transparent region belonging to the second group.

Abstract: A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L<(2Edt.sup.3 /3P).sup.1/4, wherein E is a Young's modulus of a material of the first member; d is a distance of the space between the first member and the rigid component; t is a thickness of the first member; and P is an external pressure applied to the first member; or b) for the first member adjacent to the second member: L<(2Ed't.sup.3 /3P).sup.1/4, wherein E, t and P are as defined above; and d' is a distance of the space between the first and second members.

Abstract: A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covering the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.

Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

Abstract: Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic

Abstract: A semiconductor device comprising: a semiconductor substrate having a memory cell area containing a memory cell composed of a capacitor element, and a peripheral circuit area containing a peripheral circuit for controlling the memory cell; an insulating layer covering the peripheral circuit area and being absent in the memory cell area; protective layers effective in etching of the insulating layer and covering the top surfaces and side surfaces of word line conductor patters and bit line conductor patterns in the memory cell area; a contact hole having a circumference defined by one of the protective layers that covers side surfaces of the word line conductor patterns in the memory cell area, the contact hole extending to a diffused region in the semiconductor substrate; and a storage electrode of the capacitor element being connected to the diffused region through the contact hole. A process of producing the semiconductor device is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covers the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.