Patents by Inventor Toshimi Kawahara
Toshimi Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7186575Abstract: In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.Type: GrantFiled: February 23, 2005Date of Patent: March 6, 2007Assignee: Shinko Electric Industries Co., LtdInventors: Daisuke Ito, Toshimi Kawahara
-
Publication number: 20050191772Abstract: In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.Type: ApplicationFiled: February 23, 2005Publication date: September 1, 2005Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Daisuke Ito, Toshimi Kawahara
-
Patent number: 6881611Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.Type: GrantFiled: August 8, 2000Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
-
Patent number: 6774650Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.Type: GrantFiled: March 21, 2003Date of Patent: August 10, 2004Assignee: Fujitsu LimitedInventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
-
Patent number: 6696754Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.Type: GrantFiled: August 8, 2002Date of Patent: February 24, 2004Assignee: Fujitsu LimitedInventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
-
Patent number: 6656996Abstract: Resin composition for sealing semiconductor devices, which contains a filler (A) of spherical fused silica having maximum particle size of not larger than 45 &mgr;m and may contain metal impurities having a particle size of not larger than 53 &mgr;m; and a semiconductor device sealed with the resin composition.Type: GrantFiled: May 16, 2000Date of Patent: December 2, 2003Assignees: Sumitomo Bakelite Co. Ltd., Fujitsu LimitedInventors: Yasuaki Tsutsumi, Tetsuya Mieda, Masayuki Tanaka, Toshimi Kawahara, Yukio Takigawa
-
Publication number: 20030164544Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.Type: ApplicationFiled: August 8, 2002Publication date: September 4, 2003Applicant: FUJITSU LIMITEDInventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
-
Publication number: 20030160626Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.Type: ApplicationFiled: March 21, 2003Publication date: August 28, 2003Applicant: FUJITSU LIMITEDInventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
-
Publication number: 20030132533Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.Type: ApplicationFiled: February 25, 2003Publication date: July 17, 2003Applicant: FUJITSU LIMITEDInventors: Toshimi Kawahara, Mamoru Suwa, Masanori Onodera, Syuichi Monma, Shinya Nakaseko, Takashi Hozumi
-
Patent number: 6573121Abstract: A semiconductor device includes a semiconductor element, a resin package sealing the semiconductor element, resin projections protruding downward from a mounting surface of the resin package, metallic film portions provided to the resin projections, and connecting members electrically connecting the semiconductor elements to the metallic film parts. Outer circumference surfaces of the resin package are upright surfaces defined by cutting.Type: GrantFiled: March 16, 2001Date of Patent: June 3, 2003Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Ryuji Nomoto, Toshiyuki Motooka, Kazuto Tsuji, Junichi Kasai, Toshimi Kawahara, Hideharu Sakoda, Kenji Itasaka, Terumi Kamifukumoto
-
Patent number: 6563330Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.Type: GrantFiled: March 31, 2000Date of Patent: May 13, 2003Assignee: Fujitsu LimitedInventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
-
Patent number: 6541848Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.Type: GrantFiled: October 13, 1998Date of Patent: April 1, 2003Assignee: Fujitsu LimitedInventors: Toshimi Kawahara, Mamoru Suwa, Masanori Onodera, Syuichi Monma, Shinya Nakaseko, Takashi Hozumi
-
Publication number: 20030027918Abstract: Disclosed are a resin composition for sealing semiconductor devices, which contains a filler (A) of spherical fused silica having a maximum particle size of not larger than 45 &mgr;m and may contain metal impurities having a particle size of not larger than 53 &mgr;m; and a semiconductor device sealed with the resin composition.Type: ApplicationFiled: May 16, 2000Publication date: February 6, 2003Inventors: Yasuaki Tsutsumi, Tetsuya Mieda, Masayuki Tanaka, Toshimi Kawahara, Yukio Takigawa
-
Patent number: 6511620Abstract: A method of producing semiconductor devices which have an excellent separability from a metal mold after resin encapsulation and thus eliminates the need to clean the metal mold. A metal mold for producing such semiconductor devices is also provided. According to the method of the present invention, the metal mold is first opened, and two separation sheets are disposed on dividing surfaces including cavity forming surfaces of a first metal mold and a second metal mold. A substrate is then placed on one of the separation sheets, with its semiconductor chip formed surface facing the second metal mold. An encapsulation resin is provided on the substrate placed on one of the separation sheets. The metal mold in a heated state is closed and pressed to form a resin layer for encapsulating electrodes formed on the substrate. The metal mold is again opened, and the resin-encapsulated substrate is taken out of the metal mold.Type: GrantFiled: February 23, 2000Date of Patent: January 28, 2003Assignees: Fujitsu Limited, Fujitsu Automation LimitedInventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
-
Patent number: 6507092Abstract: A semiconductor device is provided, which device includes a semiconductor chip including external terminals formed on a surface thereof and a sealing resin formed on the surface of the semiconductor chip. A contaminant film formed on the surface of said semiconductor chip has a laser-processed edge so that a peripheral portion of the surface of said semiconductor chip is bonded to the sealing resin.Type: GrantFiled: November 17, 2000Date of Patent: January 14, 2003Assignee: Fujitsu LimitedInventors: Norio Fukasawa, Takashi Hozumi, Toshimi Kawahara
-
Patent number: 6472744Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.Type: GrantFiled: May 26, 1998Date of Patent: October 29, 2002Assignee: Fujitsu LimitedInventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
-
Patent number: 6469370Abstract: In a semiconductor device of the present invention and a production method thereof, an electronic circuit is provided in a semiconductor substrate, the electronic circuit having terminals. An internal wiring pattern is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals. A protective layer is provided on the substrate, the protective layer covering the substrate. Vias are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate. An external wiring pattern is provided on the protective layer, the external wiring pattern being connected to the vias. Projection electrodes are connected to the external wiring pattern, the projection electrodes having a predetermined height above the external wiring pattern.Type: GrantFiled: February 1, 2000Date of Patent: October 22, 2002Assignee: Fujitsu LimitedInventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
-
Patent number: 6437432Abstract: A semiconductor device is provided, which device includes a semiconductor substrate including a plurality of signal pads and ground pads, an insulating film formed on the semiconductor substrate, a conductive metal film formed on the insulating film and electrically connected to the ground pads and a plurality of first interconnection lines electrically connected to the signal pads and insulated from the conductive metal film. The conductive metal film is formed over a region including the first interconnection lines in a plan view of the semiconductor device.Type: GrantFiled: December 26, 2000Date of Patent: August 20, 2002Assignee: Fujitsu LimitedInventors: Masamitsu Ikumo, Toshimi Kawahara, Norio Fukasawa, Kenichi Nagashige
-
Publication number: 20020105069Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.Type: ApplicationFiled: October 13, 1998Publication date: August 8, 2002Inventors: TOSHIMI KAWAHARA, MAMORU SUWA, MASANORI ONODERA, SYUICHI MONMA, SHINYA NAKASEKO, TAKASHI HOZUMI
-
Patent number: 6379997Abstract: A semiconductor device includes a semiconductor element, a holding substrate holding the semiconductor element, a frame body provided on the holding substrate so as to surround the semiconductor element and having a hole which communicates to a space formed between the holding substrate and the frame body and the frame body and the holding substrate form a housing, a plurality of leads having inner lead portions connected to the semiconductor element and outer lead portions extending outside the frame body, and a resin filling the space and encapsulating the semiconductor element and the inner lead portions. All of the outer lead portions extend outside the housing from one side of the housing.Type: GrantFiled: June 13, 2000Date of Patent: April 30, 2002Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Toshimi Kawahara, Sinya Nakaseko, Mitsunada Osawa, Mayumi Osumi, Hiroyuki Ishiquro, Yoshitugu Katoh, Junichi Kasai, Shinichirou Taniguchi, Yuji Sakurai