Patents by Inventor Toshimi Kawahara

Toshimi Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7186575
    Abstract: In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: March 6, 2007
    Assignee: Shinko Electric Industries Co., Ltd
    Inventors: Daisuke Ito, Toshimi Kawahara
  • Publication number: 20050191772
    Abstract: In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.
    Type: Application
    Filed: February 23, 2005
    Publication date: September 1, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Daisuke Ito, Toshimi Kawahara
  • Patent number: 6881611
    Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
  • Patent number: 6774650
    Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
  • Patent number: 6696754
    Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
  • Patent number: 6656996
    Abstract: Resin composition for sealing semiconductor devices, which contains a filler (A) of spherical fused silica having maximum particle size of not larger than 45 &mgr;m and may contain metal impurities having a particle size of not larger than 53 &mgr;m; and a semiconductor device sealed with the resin composition.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: December 2, 2003
    Assignees: Sumitomo Bakelite Co. Ltd., Fujitsu Limited
    Inventors: Yasuaki Tsutsumi, Tetsuya Mieda, Masayuki Tanaka, Toshimi Kawahara, Yukio Takigawa
  • Publication number: 20030164544
    Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
    Type: Application
    Filed: August 8, 2002
    Publication date: September 4, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
  • Publication number: 20030160626
    Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.
    Type: Application
    Filed: March 21, 2003
    Publication date: August 28, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
  • Publication number: 20030132533
    Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.
    Type: Application
    Filed: February 25, 2003
    Publication date: July 17, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Toshimi Kawahara, Mamoru Suwa, Masanori Onodera, Syuichi Monma, Shinya Nakaseko, Takashi Hozumi
  • Patent number: 6573121
    Abstract: A semiconductor device includes a semiconductor element, a resin package sealing the semiconductor element, resin projections protruding downward from a mounting surface of the resin package, metallic film portions provided to the resin projections, and connecting members electrically connecting the semiconductor elements to the metallic film parts. Outer circumference surfaces of the resin package are upright surfaces defined by cutting.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: June 3, 2003
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Ryuji Nomoto, Toshiyuki Motooka, Kazuto Tsuji, Junichi Kasai, Toshimi Kawahara, Hideharu Sakoda, Kenji Itasaka, Terumi Kamifukumoto
  • Patent number: 6563330
    Abstract: A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: May 13, 2003
    Assignee: Fujitsu Limited
    Inventors: Shigeyuki Maruyama, Daisuke Koizumi, Naoyuki Watanabe, Yoshito Konno, Eiji Yoshida, Toshiyuki Honda, Toshimi Kawahara, Kenichi Nagashige
  • Patent number: 6541848
    Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: April 1, 2003
    Assignee: Fujitsu Limited
    Inventors: Toshimi Kawahara, Mamoru Suwa, Masanori Onodera, Syuichi Monma, Shinya Nakaseko, Takashi Hozumi
  • Publication number: 20030027918
    Abstract: Disclosed are a resin composition for sealing semiconductor devices, which contains a filler (A) of spherical fused silica having a maximum particle size of not larger than 45 &mgr;m and may contain metal impurities having a particle size of not larger than 53 &mgr;m; and a semiconductor device sealed with the resin composition.
    Type: Application
    Filed: May 16, 2000
    Publication date: February 6, 2003
    Inventors: Yasuaki Tsutsumi, Tetsuya Mieda, Masayuki Tanaka, Toshimi Kawahara, Yukio Takigawa
  • Patent number: 6511620
    Abstract: A method of producing semiconductor devices which have an excellent separability from a metal mold after resin encapsulation and thus eliminates the need to clean the metal mold. A metal mold for producing such semiconductor devices is also provided. According to the method of the present invention, the metal mold is first opened, and two separation sheets are disposed on dividing surfaces including cavity forming surfaces of a first metal mold and a second metal mold. A substrate is then placed on one of the separation sheets, with its semiconductor chip formed surface facing the second metal mold. An encapsulation resin is provided on the substrate placed on one of the separation sheets. The metal mold in a heated state is closed and pressed to form a resin layer for encapsulating electrodes formed on the substrate. The metal mold is again opened, and the resin-encapsulated substrate is taken out of the metal mold.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: January 28, 2003
    Assignees: Fujitsu Limited, Fujitsu Automation Limited
    Inventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
  • Patent number: 6507092
    Abstract: A semiconductor device is provided, which device includes a semiconductor chip including external terminals formed on a surface thereof and a sealing resin formed on the surface of the semiconductor chip. A contaminant film formed on the surface of said semiconductor chip has a laser-processed edge so that a peripheral portion of the surface of said semiconductor chip is bonded to the sealing resin.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: January 14, 2003
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Takashi Hozumi, Toshimi Kawahara
  • Patent number: 6472744
    Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: October 29, 2002
    Assignee: Fujitsu Limited
    Inventors: Mitsutaka Sato, Tetsuya Fujisawa, Shigeyuki Maruyama, Junichi Kasai, Toshimi Kawahara, Toshio Hamano, Yoshihiro Kubota, Mitsunada Osawa, Yoshiyuki Yoneda, Kazuto Tsuji, Hirohisa Matsuki
  • Patent number: 6469370
    Abstract: In a semiconductor device of the present invention and a production method thereof, an electronic circuit is provided in a semiconductor substrate, the electronic circuit having terminals. An internal wiring pattern is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals. A protective layer is provided on the substrate, the protective layer covering the substrate. Vias are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate. An external wiring pattern is provided on the protective layer, the external wiring pattern being connected to the vias. Projection electrodes are connected to the external wiring pattern, the projection electrodes having a predetermined height above the external wiring pattern.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: October 22, 2002
    Assignee: Fujitsu Limited
    Inventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
  • Patent number: 6437432
    Abstract: A semiconductor device is provided, which device includes a semiconductor substrate including a plurality of signal pads and ground pads, an insulating film formed on the semiconductor substrate, a conductive metal film formed on the insulating film and electrically connected to the ground pads and a plurality of first interconnection lines electrically connected to the signal pads and insulated from the conductive metal film. The conductive metal film is formed over a region including the first interconnection lines in a plan view of the semiconductor device.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: August 20, 2002
    Assignee: Fujitsu Limited
    Inventors: Masamitsu Ikumo, Toshimi Kawahara, Norio Fukasawa, Kenichi Nagashige
  • Publication number: 20020105069
    Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.
    Type: Application
    Filed: October 13, 1998
    Publication date: August 8, 2002
    Inventors: TOSHIMI KAWAHARA, MAMORU SUWA, MASANORI ONODERA, SYUICHI MONMA, SHINYA NAKASEKO, TAKASHI HOZUMI
  • Patent number: 6379997
    Abstract: A semiconductor device includes a semiconductor element, a holding substrate holding the semiconductor element, a frame body provided on the holding substrate so as to surround the semiconductor element and having a hole which communicates to a space formed between the holding substrate and the frame body and the frame body and the holding substrate form a housing, a plurality of leads having inner lead portions connected to the semiconductor element and outer lead portions extending outside the frame body, and a resin filling the space and encapsulating the semiconductor element and the inner lead portions. All of the outer lead portions extend outside the housing from one side of the housing.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: April 30, 2002
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Toshimi Kawahara, Sinya Nakaseko, Mitsunada Osawa, Mayumi Osumi, Hiroyuki Ishiquro, Yoshitugu Katoh, Junichi Kasai, Shinichirou Taniguchi, Yuji Sakurai