Patents by Inventor Toshimi Kohmura
Toshimi Kohmura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8115307Abstract: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.Type: GrantFiled: August 12, 2009Date of Patent: February 14, 2012Assignee: Intel CorporationInventors: Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura
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Publication number: 20090294992Abstract: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.Type: ApplicationFiled: August 12, 2009Publication date: December 3, 2009Applicant: Intel CorporationInventors: Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura
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Patent number: 7592202Abstract: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.Type: GrantFiled: March 31, 2006Date of Patent: September 22, 2009Assignee: Intel CorporationInventors: Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura
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Patent number: 7394159Abstract: Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.Type: GrantFiled: February 23, 2005Date of Patent: July 1, 2008Assignee: Intel CorporationInventors: Hideki Goto, Toshimi Kohmura
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Publication number: 20070232050Abstract: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura
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Publication number: 20060186537Abstract: Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.Type: ApplicationFiled: February 23, 2005Publication date: August 24, 2006Inventors: Hideki Goto, Toshimi Kohmura
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Publication number: 20060172061Abstract: Numerous embodiments of a method and apparatus for forming a substrate are disclosed. In one embodiment, a method for substrate fabrication comprises imprinting one or more features on a substrate, depositing a protective layer on a substantial portion of the top surface of the substrate, applying a metal filled paste to at least a portion of the one or more features, removing a substantial portion of the protective layer, and curing the metal filled paste to form one or more conductive structures.Type: ApplicationFiled: June 5, 2003Publication date: August 3, 2006Inventors: Toshimi Kohmura, Michael Walk
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Patent number: 6407929Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).Type: GrantFiled: June 29, 2000Date of Patent: June 18, 2002Assignee: Intel CorporationInventors: Aaron Dean Hale, Michael Walk, David G. Figueroa, Joan K. Vrtis, Toshimi Kohmura
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Patent number: 6303873Abstract: An inexpensive electronic part module and a process for manufacturing the same, wherein an inexpensive thermoplastic resin is used as the substrate of the circuit board. In order to electrically connect the solder bumps of an electronic part such as an IC chip to a connection pattern, without forming connection holes in the substrate, the substrate is melted and the solder bumps are passed through the substrate by pressing the electronic part against the substrate in a state that the electronic part is heated. The substrate itself can be utilized as an adhesive. The solder bumps 2 are passed through the substrate 4 and contacted with the connection pattern 5 by pressing the solder bumps 2 against the substrate 4 in a state that the electronic part 3 is heated to a temperature higher than the melting point of the thermoplastic resin and lower than the melting point of the solder bumps 2.Type: GrantFiled: April 29, 1998Date of Patent: October 16, 2001Assignee: Ibiden Co., Ltd.Inventors: Mikio Mori, Toshimi Kohmura
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Patent number: 5956237Abstract: A primary printed wiring board includes: secondary printed wiring boards arranged in plural lines; main plated leads formed between the plural lines of secondary printed wiring boards; and auxiliary plated leads which connect patterns forming the secondary printed wiring boards to the main plated leads. In the primary printed wiring board, each main plated lead is zig-zagged to provide forward lines and backward lines which are laid respectively on both sides of a cutting line with respect to the pattern, and the auxiliary plated leads are connected to the backward lines.With the primary printed wiring board thus designed, the auxiliary plated leads can be isolated from one another without being processed by blanking. That is, by cutting the board along a predetermined cutting line or lines, the auxiliary plated leads can be separated from the main plated leads and isolated from one another.Type: GrantFiled: June 24, 1996Date of Patent: September 21, 1999Assignee: IBIDEN Co., Ltd.Inventors: Toshimi Kohmura, Yasuhiro Horiba, Hisao Kato
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Patent number: 5822194Abstract: The present invention is to provide an electronic part mounting device including: a lamination body composed of a circuit board and a structural member; an electronic part attached in an opening formed in the lamination body; and an encapsulant layer to encapsulate the electronic part, wherein an outer circumferential line of the opening is arranged inside an outer circumferential line of the encapsulant layer. Due to the foregoing arrangement, in the electronic part mounting device of the present invention, even if the device is bent, the encapsulant layer to encapsulate the electronic part is engaged with the circuit board or the structural member arranged inside the outer circumferential line of the encapsulant layer, so that electronic parts are prevented from coming off. Further, the manufacturing process is simple. Therefore, the cost of the electronic part mounting device can be greatly reduced.Type: GrantFiled: September 30, 1996Date of Patent: October 13, 1998Assignee: Ibiden Co., Ltd.Inventors: Yasuhiro Horiba, Toshimi Kohmura
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Patent number: 5160783Abstract: An epoxy resin-impregnated glass cloth sheet having an adhesive layer provided on at least one side of the surface thereof, characterized in that (A) said epoxy resin-impregnated glass cloth sheet is formed by impregnating glass cloth with a curable epoxy resin composition and curing it, said curable epoxy resin composition comprising an epoxy resin represented by the following structural formula (I), a brominated epoxy resin and a curing agent for epoxy resin in such an amount that the content of the epoxy resin represented by the following structural formula (I) is 5 to 50% by weight based on the amount of the entire epoxy resins and the content of bromine atom is 14 to 30% by weight based on the combined amount of the entire epoxy resins and the curing agent for epoxy resin; and (B) said adhesive layer is composed of a curable epoxy resin composition comprising an epoxy resin represented by the following structural formula (I), a brominated epoxy resin, an acrylonitrile/butadiene copolymer having carboxylType: GrantFiled: December 19, 1990Date of Patent: November 3, 1992Assignee: Mitsubishi Petrochemical Co., Ltd.Inventors: Yousui Nemoto, Akiyoshi Itoh, Toshimi Kohmura, Yasuhiro Horiba