Abstract: There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the

Abstract: There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the

Abstract: A pattern generator for generating a test pattern that has a repetition rate higher than the basic repetition rate thereof to test a synchronous memory. The test pattern to be provided to a memory under test can be accurately modified by inverting the pattern data as a function of address data.

Abstract: A fail analysis device is to count the number of fails with respect to a memory under test detected during the test.

Abstract: A pattern generator facilitates the pattern generation of an electronics device to be measured such as SDRAM where each input and output signal cycle is not matched. The pattern generator includes a first address signal delay section that applies a cycle delay to a first address signal based on the number set in a first delay register, a second address signal delay section that applies a cycle delay to a second address signal based on the number set in a second delay register, a data signal delay section that applies a cycle delay to a data signal based on the number set in a data delay register, a control signal delay section that applies cycle delay to a control signal based on the number set in a control delay register.

Abstract: A high speed pattern generator is disclosed that can generate a test pattern at high speed for an electronics device to be tested, such as a flash memory where the test flow varies depending on the test results. The pattern generator includes an address generator for generating address data of the test pattern and the address generator has a pipeline wherein a plurality of instructions are executed in sequential stages at the same time, an operation control memory that stores part of the instructions to be processed in the address generator, a save register that stores branch destination data in a sequence control section in response to a match signal from a comparator wherein the sequence control section accesses the operation control memory to read the instructions, and an inhibit gate that prevents an initial clock generator from generating an initial clock for driving the pipeline in the address generator in response to the match signal.

Abstract: A test data pattern, an address pattern, and a control signal are supplied from a pattern generator to a test memory. Data read from the test memory is compared with expected data by an XOR gate. When they match, a compared result that represents pass is output. When they mismatch, a compared result that represents fail is output. A match signal WC detected by the XOR gate is held in a register. The register outputs an inhibition signal to an inhibition gate of the test memory. Thus, a write enable signal WE is inhibited from being supplied to the test memory. In addition, the inhibition signal is supplied to a compared result inhibition gate. The compared result inhibition gate causes the compared result to be passed and prevents the test memory from being excessively written.

Abstract: A failure memory device for compressing, in bit, failure data of a multi-bit memory under test to store the compressed failure data in a failure memory is provided, which is capable of generating a mask data. Failure data obtained from the logical comparison results of data written in a four bit memory under test are supplied to AND-OR circuits 27.sub.1 -27.sub.4 of a compression circuit 30 through input terminals 21.sub.1 -21.sub.4 respectively. In each AND-OR circuit, ANDs between the failure data and four bit compression data set in registers 26.sub.1 -26.sub.4 are performed respectively, and the ANDs are ORed. The ORed outputs of the respective AND-OR circuits are supplied to input pins 22.sub.1 -22.sub.4 of a failure memory 17. Readout data from output pins 23.sub.1 -23.sub.4 of the failure memory are supplied to AND-OR circuits 31.sub.1 -31.sub.4 of an expansion circuit 25 respectively. In the AND-OR circuit 31.sub.1, ANDs between the read out data and the first bit data of the registers 26.sub.1 -26.