Abstract: A data receiving circuit includes a clock generation circuit, a skew adjustment circuit, a leading edge detecting circuit, and a control circuit. The clock generation circuit generates a clock signal and a decision clock signal transitioning from a second level to a first level at a time point advancing by a time of ½ of the bit cycle with respect to the clock signal, according to the received reference clock signal. The skew adjustment circuit generates a skew adjustment data signal by delaying the received data signal through a delay circuit. The leading edge detecting circuit detects a leading edge of one bit of the skew adjustment data signal to generate a leading edge detection signal. The control circuit controls the delay time of the delay circuit based on the decision clock signal and the leading edge detection signal.

Abstract: A detection circuit, provided in a gamma buffer circuit that includes at least one transistor that receives the application of a first voltage and generates gradation voltages on the basis of a plurality of gamma voltages, includes: a first comparison circuit that compares the largest gamma voltage with a substrate potential of the transistor and outputs a first comparison result signal, a second comparison circuit that includes an inverter which is operable under a second voltage as a source voltage, compares a threshold voltage of the inverter with the substrate potential, and outputs a second comparison result signal; and a detection result output circuit for outputting a detection result showing if the voltage decrease or power discontinuity of the first voltage is occurring on the basis of the first comparison result signal and the second comparison result signal.

Abstract: A detection circuit, provided in a gamma buffer circuit that includes at least one transistor that receives the application of a first voltage and generates gradation voltages on the basis of a plurality of gamma voltages, includes: a first comparison circuit that compares the largest gamma voltage with a substrate potential of the transistor and outputs a first comparison result signal, a second comparison circuit that includes an inverter which is operable under a second voltage as a source voltage, compares a threshold voltage of the inverter with the substrate potential, and outputs a second comparison result signal; and a detection result output circuit for outputting a detection result showing if the voltage decrease or power discontinuity of the first voltage is occurring on the basis of the first comparison result signal and the second comparison result signal.

Abstract: An AD (analog-to-digital) conversion circuit includes a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time.

Abstract: An AD (analog-to-digital) conversion circuit includes a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time.

Abstract: An audio output device and method capable of preventing generation of pop noise by a relatively simple and small-sized circuit configuration and control timing. A D/A converter converts a digital audio signal to an analog audio signal. A non-inverting amplifier amplifies the analog audio signal. A signal output from the non-inverting amplifier is amplified by inverting amplifiers of two stages with a first timing. A signal output from an inverting amplifier is input to a speaker amplifier by a switch. The output signal of the inverting amplifier is output to a speaker with a second timing subsequent to the first timing. The output signal of the inverting amplifier is amplified by the speaker amplifier and output to the speaker. With a third timing subsequent to the second timing, the output of each of the inverting amplifiers is stopped and the output of the speaker amplifier is stopped.

Abstract: Disclosed is a signal amplifying device which includes an overcurrent detection circuit, a first inverting amplifying circuit amplifying an input signal, and a second inverting amplifying circuit amplifying an output of the first inverting amplifying circuit. The overcurrent detection circuit includes a comparison circuit and a decision circuit. The comparison circuit compares the voltage of the input signal with the voltage of an output of the second inverting amplifying circuit, and generates a signal responsive to the comparison result. The decision circuit detects overcurrent from the signal output by the comparison circuit.

Abstract: An audio output device and method capable of preventing generation of pop noise by a relatively simple and small-sized circuit configuration and control timing. A D/A converter converts a digital audio signal to an analog audio signal. A non-inverting amplifier amplifies the analog audio signal. A signal output from the non-inverting amplifier is amplified by inverting amplifiers of two stages with a first timing. A signal output from an inverting amplifier is input to a speaker amplifier by a switch. The output signal of the inverting amplifier is output to a speaker with a second timing subsequent to the first timing. The output signal of the inverting amplifier is amplified by the speaker amplifier and output to the speaker. With a third timing subsequent to the second timing, the output of each of the inverting amplifiers is stopped and the output of the speaker amplifier is stopped.

Abstract: The present invention provides a multi-input A/D converter circuit capable of shorting a conversion time without increasing its layout area and current consumption. When a most significant bit of a binary counter is “L”, individual input signals are sampled by a sample and hold unit, and digital signals held in respective data holders are sequentially selected by a selector. When the most significant bit is brought to “H”, the respective input signals are held as analog signals and compared with each of reference voltages produced corresponding to a digital signal by a DAC. When decision signals outputted from comparators are changed from “L” to “H”, the digital signal at that time is held in the individual data holders as digital signals.

Abstract: The present invention provides a multi-input A/D converter circuit capable of shorting a conversion time without increasing its layout area and current consumption. When a most significant bit of a binary counter is “L”, individual input signals are sampled by a sample and hold unit, and digital signals held in respective data holders are sequentially selected by a selector. When the most significant bit is brought to “H”, the respective input signals are held as analog signals and compared with each of reference voltages produced corresponding to a digital signal by a DAC. When decision signals outputted from comparators are changed from “L” to “H”, the digital signal at that time is held in the individual data holders as digital signals.

Abstract: A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitored clock by delaying the to-be-monitored clock by a predetermined time, a latch circuit which detects based on the to-be-monitored clock and the delayed synchronous to-be-monitored clock that a value of a decrease in a pulse width to be determined by a pulse duty of the to-be-monitored clock becomes smaller than the predetermined time, and a flip-flop circuit which samples an output signal of the latch circuit based on the to-be-monitored clock.

Abstract: A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitored clock by delaying the to-be-monitored clock by a predetermined time, a latch circuit which detects based on the to-be-monitored clock and the delayed synchronous to-be-monitored clock that a value of a decrease in a pulse width to be determined by a pulse duty of the to-be-monitored clock becomes smaller than the predetermined time, and a flip-flop circuit which samples an output signal of the latch circuit based on the to-be-monitored clock.

Abstract: An operational amplification circuit having no crossover distortion includes a pair of differential amplification circuits, a pair of level shift circuits, a pair of current source circuits, and an output circuit. Each of the differential amplification circuits includes two MOS transistors having gates connected to a respective pair of input terminals. The differential amplification circuits generate first and second signals. The level shift circuits connected to the differential amplification circuits shift the level of the first and second signals. Each of the level shift circuits includes complementary MOS transistors. The current source circuits supply a predetermined current to one of the transistors of the level shift circuits. The output circuit is connected to the level shift circuits for generating an output signal.