Patents by Inventor Toshimichi Shimatani

Toshimichi Shimatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5025441
    Abstract: A key telephone system for use in PCM telecommunications includes an office line communication units, an extension interface unit, a receiving unit, an extension communication unit, and an information transmitting and receiving unit.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: June 18, 1991
    Assignee: Iwatsu Electric Company, Ltd.
    Inventors: Masaharu Kamigaki, Hironobu Oshikata, Yoshihiro Kawata, Nobuyasu Shiga, Hideharu Omori, Masayuki Kawashima, Toshimichi Shimatani
  • Patent number: 4905258
    Abstract: There is disclosed a data circuit-terminating equipment (DCE) which connects a start-stop synchronous data terminal equipment (DTE) which is not synchronized with a PCM transmission line having various speeds. Further the DCE can satisfy recommendations of the V25 bis of CCITT. The DCE includes a start-stop synchronizing circuit to deliver a sampled request-to-send signal RS, a sampled send data and to transmit a clear-to-send signal CS to the DTE, a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make the sampled send data match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE.
    Type: Grant
    Filed: August 8, 1988
    Date of Patent: February 27, 1990
    Assignee: Iwatsu Electric Co., Ltd.
    Inventors: Toshimichi Shimatani, Yoshihiro Kawata, Masaharu Kamigaki
  • Patent number: 4815099
    Abstract: There is disclosed a data circuit-terminating equipment (DCE) which connects an asynchronous data terminal equipment (DTE) with a PCM trnsmission line having various speeds. Further the DCE can satisfy recomendations of the V25 bis of CCITT. The DCE includes a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make data from the DTE match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE.
    Type: Grant
    Filed: May 27, 1988
    Date of Patent: March 21, 1989
    Assignee: Iwatsu Electric Co., Ltd.
    Inventors: Toshimichi Shimatani, Yoshihiro Kawata, Masayuki Kawashima, Hideharu Omori
  • Patent number: 4805165
    Abstract: A telecommunications network such as a key telephone system having n terminal devices such as telephone sets which are notionally divided into m groups, for the time division multiplex transmission and reception of m groups of n channels of data, where n is at least six and m is at least three. The invention particularly features a method of, and apparatus for, demultiplexing the multiplex data signal prior to reception by the terminal devices. The multiplex data signal is such that the n channels of data are assigned respectively to a set of n consecutive time slots making up one frame. Under the direction of a control circuit the multiplexed m groups of n channels of data are written onto m groups of n demultiplexing shift registers, respectively, at a relatively high speed.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: February 14, 1989
    Assignee: Iwatsu Electric Co., Ltd.
    Inventors: Masataka Kawamura, Toshimichi Shimatani
  • Patent number: 4694470
    Abstract: A data transmission circuit is disclosed which is arranged so that when transmitting data and control signals of a terminal equipment accommodated in a transmission line of 64 Kbps channels through use of a multi-frame arrangement, the data is assigned to a required number of bits in a predetermined number of frames in the multi-frame or adjacent ones of the predetermined number of bits and at least one synchronization flag bit and various control signals are assigned to the remaining bits but a request to send signal and the synchronization being assigned to one of the remaining bits according to the logic OR of their succeeding sampled values, whereby data of different transmission speeds can be transmitted by the same circuit.
    Type: Grant
    Filed: November 8, 1985
    Date of Patent: September 15, 1987
    Assignee: Iwatsu Electric Co. Ltd.
    Inventors: Toshimichi Shimatani, Yoshihiro Kawata