Patents by Inventor Toshimichi Shintani

Toshimichi Shintani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11530912
    Abstract: A distance measurement device includes a light-emitting-unit that emits irradiation light toward an object; a light-receiving unit that receives reflected light from the object; a distance-calculation unit that calculates a distance to the object based on a transmission time of the reflected light received; a posture-adjustment mechanism that adjusts a posture of at least the light-receiving-unit; and a posture-controller that drives the posture-adjustment mechanism. The light-receiving unit is formed of a two-dimensional sensor in which a plurality of pixels are two-dimensionally arrayed, and the distance-calculation unit calculates two-dimensional distance data from received light data in each of the pixels of the two-dimensional sensor.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 20, 2022
    Assignee: HITACHI-LG DATA STORAGE, INC.
    Inventors: Hiroshi Ogasawara, Toshimichi Shintani, Takahiro Komaki, Hisataka Sugiyama
  • Patent number: 11531102
    Abstract: A distance measurement image pickup apparatus has two measurement periods. In a first distance measurement period, short pulsed light (1T) is irradiated, and exposure is performed in a plurality of exposure periods (A, B, and C) in which exposure timings are shifted. In each exposure period, an exposure gate is opened a plurality of times to perform repetitive exposure, and a first non-exposure period is provided from when a last exposure gate is closed until subsequent pulsed light is irradiated. In a second distance measurement period, long pulsed light (4T) is irradiated, and exposure is performed in a plurality of exposure periods (A, B, and C) in which exposure timings are shifted. In each exposure period, exposure is performed by opening the exposure gate only once, and a second non-exposure period is provided from when a last exposure gate is closed until subsequent pulsed light is irradiated.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 20, 2022
    Assignee: HITACHI-LG DATA STORAGE, INC.
    Inventors: Toshimasa Kamisada, Kozo Masuda, Hisataka Sugiyama, Toshimichi Shintani
  • Publication number: 20210285757
    Abstract: A distance measurement device includes a light-emitting-unit that emits irradiation light toward an object; a light-receiving unit that receives reflected light from the object; a distance-calculation unit that calculates a distance to the object based on a transmission time of the reflected light received; a posture-adjustment mechanism that adjusts a posture of at least the light-receiving-unit; and a posture-controller that drives the posture-adjustment mechanism. The light-receiving unit is formed of a two-dimensional sensor in which a plurality of pixels are two-dimensionally arrayed, and the distance-calculation unit calculates two-dimensional distance data from received light data in each of the pixels of the two-dimensional sensor.
    Type: Application
    Filed: November 30, 2020
    Publication date: September 16, 2021
    Inventors: Hiroshi OGASAWARA, Toshimichi SHINTANI, Takahiro KOMAKI, Hisataka SUGIYAMA
  • Publication number: 20200110177
    Abstract: A distance measurement image pickup apparatus has two measurement periods. In a first distance measurement period, short pulsed light (1T) is irradiated, and exposure is performed in a plurality of exposure periods (A, B, and C) in which exposure timings are shifted. In each exposure period, an exposure gate is opened a plurality of times to perform repetitive exposure, and a first non-exposure period is provided from when a last exposure gate is closed until subsequent pulsed light is irradiated. In a second distance measurement period, long pulsed light (4T) is irradiated, and exposure is performed in a plurality of exposure periods (A, B, and C) in which exposure timings are shifted. In each exposure period, exposure is performed by opening the exposure gate only once, and a second non-exposure period is provided from when a last exposure gate is closed until subsequent pulsed light is irradiated.
    Type: Application
    Filed: August 27, 2019
    Publication date: April 9, 2020
    Inventors: Toshimasa KAMISADA, Kozo MASUDA, Hisataka SUGIYAMA, Toshimichi SHINTANI
  • Patent number: 9490428
    Abstract: Technology capable of improving performance of a phase-change memory is provided. A recording/reproducing film contains Sn (tin), Sb (antimony), and Te (tellurium) and also contains an element X having a bonding strength with Te stronger than a bonding strength between Sn and Te and a bonding strength between Sb and Te. Here, the recording/reproducing film has a (SnXSb)Te alloy phase, and this (SnXSb)Te alloy phase includes a self-assembled superlattice structure.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: November 8, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Soeya, Toshimichi Shintani, Takahiro Odaka
  • Patent number: 9177640
    Abstract: A phase-change device capable of realizing a multi-level record in a superlattice phase-change memory cell in which a superlattice phase-change material is used as a recording film, and thereby achieving the reduction in power consumption and the capacity increase is provided. To a phase-change memory cell composed of GeTe/Sb2Te3 superlattice or SnTe/Sb2Te3 superlattice, a SET pulse is once applied to form a SET state (low resistance state). Thereafter, recording pulses having respectively different voltage values between a voltage value forming the SET state and a voltage value forming a RESET state (high resistance state) are respectively applied to the superlattice phase-change memory cell twice or more. In this manner, a read resistance (SET resistance) corresponding to a recording pulse (SET pulse) and read resistances corresponding to each of the recording pulses are obtained, so that the multi-level record can be realized.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: November 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Toshimichi Shintani, Susumu Soeya
  • Patent number: 9082970
    Abstract: A phase-change memory and a semiconductor recording reproducing device capable of reducing consumed power are provided. A SnxTe100-x/Sb2Te3 SL film obtained by depositing a SnxTe100-x film and a Sb2Te3 film layer by layer contains a SnTe/Sb2Te3 superlattice phase formed of SnTe and Sb2Te3, a SnSbTe alloy phase, and a Te phase. The SnTe/Sb2Te3 superlattice phase is diluted by the SnSbTe alloy phase and the Te phase. Here, X of the SnxTe100-x film is represented by 4 at. %?X?55 at. %.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 14, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Soeya, Takahiro Odaka, Toshimichi Shintani, Junji Tominaga
  • Patent number: 9082955
    Abstract: An object of the present invention is to provide a technique for suppressing thermal disturbance of a phase change memory device having a three-dimensional structure. In the phase change memory device having a three-dimensional structure, a material having a high thermal conductivity is used as a gate insulation film of a MOS transistor for selection, and causes heat transmitted to a Si channel layer from a phase change recording film to successfully diffuse to a gate electrode. In this way, since heat generated from a recording bit diffuses to a non-selected bit adjacent to it, it is possible to suppress thermal disturbance. BN, Al2O3, AlN, TiO2, Si3N4, ZnO and the like are useful as a gate insulation film having a high thermal conductivity.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 14, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Toshimichi Shintani, Takahiro Morikawa, Takahiro Odaka
  • Publication number: 20150144865
    Abstract: Technology capable of improving performance of a phase-change memory is provided. A recording/reproducing film contains Sn (tin), Sb (antimony), and Te (tellurium) and also contains an element X having a bonding strength with Te stronger than a bonding strength between Sn and Te and a bonding strength between Sb and Te. Here, the recording/reproducing film has a (SnXSb)Te alloy phase, and this (SnXSb)Te alloy phase includes a self-assembled superlattice structure.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 28, 2015
    Inventors: Susumu Soeya, Toshimichi Shintani, Takahiro Odaka
  • Patent number: 8982682
    Abstract: An information storage device has small compartments for storing information in a solid body and can be used as a memory medium. The solid body can have at least one pair of parallel planar portions on its surface. The information is divided into bits and stored in discrete minute areas that are distributed three-dimensionally inside the memory medium. The data can be converted into a digital format for storage to regulate the number of ā€˜1sā€™ recorded in a direction of the memory medium.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Takao Watanabe, Toshimichi Shintani
  • Publication number: 20140376307
    Abstract: A phase-change device capable of realizing a multi-level record in a superlattice phase-change memory cell in which a superlattice phase-change material is used as a recording film, and thereby achieving the reduction in power consumption and the capacity increase is provided. To a phase-change memory cell composed of GeTe/Sb2Te3 superlattice or SnTe/Sb2Te3 superlattice, a SET pulse is once applied to form a SET state (low resistance state). Thereafter, recording pulses having respectively different voltage values between a voltage value forming the SET state and a voltage value forming a RESET state (high resistance state) are respectively applied to the superlattice phase-change memory cell twice or more. In this manner, a read resistance (SET resistance) corresponding to a recording pulse (SET pulse) and read resistances corresponding to each of the recording pulses are obtained, so that the multi-level record can be realized.
    Type: Application
    Filed: January 24, 2014
    Publication date: December 25, 2014
    Inventors: Toshimichi Shintani, Susumu Soeya
  • Publication number: 20140252304
    Abstract: A phase-change memory and a semiconductor recording/reproducing device capable of reducing consumed power are provided. A SnxTe100-x/Sb2Te3 SL film obtained by depositing a SnxTe100-x film and a Sb2Te3 film layer by layer contains a SnTe/Sb2Te3 superlattice phase formed of SnTe and Sb2Te3, a SnSbTe alloy phase, and a Te phase. The SnTe/Sb2Te3 superlattice phase is diluted by the SnSbTe alloy phase and the Te phase. Here, X of the SnxTe100-x film is represented by 4 at. %?X?55 at. %.
    Type: Application
    Filed: October 10, 2013
    Publication date: September 11, 2014
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Susumu Soeya, Takahiro Odaka, Toshimichi Shintani, Junji Tominaga
  • Patent number: 8830740
    Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
  • Patent number: 8803119
    Abstract: A technique capable of improving performances of a semiconductor memory device provided with a recording film having a super lattice structure is provided. The semiconductor memory device records information by changing an electric resistance of a recording film by use of a change in an atomic arrangement of the recording film. Moreover, the recording film is provided with a stacked layer portion in which a first crystal layer and a second crystal layer made of chalcogen compounds having respectively different compositions are stacked, an orientation layer that enhances an orientation of the stacked layer portion, and an adhesive layer that improves the flatness of the orientation layer.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: August 12, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Takahiro Morikawa, Toshimichi Shintani
  • Patent number: 8735865
    Abstract: For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: May 27, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Minemura, Yumiko Anzai, Takahiro Morikawa, Toshimichi Shintani, Yoshitaka Sasago
  • Publication number: 20130141968
    Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
    Type: Application
    Filed: August 26, 2011
    Publication date: June 6, 2013
    Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
  • Publication number: 20130048938
    Abstract: An object of the present invention is to provide a technique for suppressing thermal disturbance of a phase change memory device having a three-dimensional structure. In the phase change memory device having a three-dimensional structure, a material having a high thermal conductivity is used as a gate insulation film of a MOS transistor for selection, and causes heat transmitted to a Si channel layer from a phase change recording film to successfully diffuse to a gate electrode. In this way, since heat generated from a recording bit diffuses to a non-selected bit adjacent to it, it is possible to suppress thermal disturbance. BN, Al2O3, AlN, TiO2, Si3N4, ZnO and the like are useful as a gate insulation film having a high thermal conductivity.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 28, 2013
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshimichi Shintani, Takahiro Morikawa, Takahiro Odaka
  • Patent number: 8169866
    Abstract: By referring to a table of reproducing conditions and medium specific parameters, stored in an optical disc or optical disc apparatus and/or generated by the optical disc apparatus, the medium specific parameters to be used for performing reproducing power adjustment are changed in accordance with the reproducing condition to execute reproducing power adjustment.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 1, 2012
    Assignee: Hitachi Comsumer Electronics Co., Ltd.
    Inventors: Soichiro Eto, Toshimichi Shintani, Hiroyuki Minemura
  • Patent number: 8147941
    Abstract: In forming a space layer of a multi-formation-layer recording medium, there are provided a medium having a high precision in a thickness of the space layer and its manufacturing process. In the multi-formation-layer recording medium wherein at least two pairs of an information recording layer and a translucency spacer are layered on a substrate having physical patterns composed of an optical spot groove and/or pits on the surface, an average thickness of the translucency spacers in an information zone is 15 ?m or less, and a difference in spacer thickness between a minimum value and a maximum value is 2 ?m or less.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yumiko Anzai, Junko Ushiyama, Toshimichi Shintani
  • Patent number: 8134905
    Abstract: In an information memory apparatus having minute areas for storing information arranged in x, y and z directions three-dimensionally, parallel rays are irradiated to a memory area MA in a direction perpendicular to a z-axis to take projection images of the memory area MA while rotating the memory area MA around the z-axis little by little. The light rays irradiated at this time have a size which covers at least a direction of an x-y plane of the memory area. A computation unit PU finds data and addresses of minute areas distributed three-dimensionally by performing computation based upon the principle of computer tomography on the projection images. As for data writing, a change is given to optical transmissivity or light emission characteristics by irradiating laser light focused by a lens OL placed outside the memory area to a desired minute area and causing heat denaturation within the pertinent minute area.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: March 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Takao Watanabe, Toshimichi Shintani, Takeshi Maeda, Akemi Hirotsune, Tomonori Sekiguchi