Patents by Inventor Toshimitsu Masuzawa

Toshimitsu Masuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6735730
    Abstract: A test controller 4 has a test plan generating unit 11 for generating a test plan of a data path 2 which is formed to have a fixed control testability in which a test plan constituted by three phases, that is, the propagation of a test vector to a data input, the execution of a test and the propagation of an output response is present for each test object module. Thus, an integrated circuit is capable of supplying a test plan as a time series of a control signal to a control input of a data path, shortening a test execution time and generating the test plan at the normal operation speed of the circuit, thereby carrying out a test at an actual operation speed and an integrated circuit designing method.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 11, 2004
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hideo Fujiwara, Toshimitsu Masuzawa, Satoshi Ohtake
  • Patent number: 6334200
    Abstract: Apparatus for testing integrated circuits containing a controller or other sequential circuit at actual operating speed while minimizing the length of the test sequence and achieving high fault coverage are provided. The states of a state register are assumed controllable and observable, and a set of test patterns is obtained for a combinational circuit not containing said state register. An invalid-state generation logic circuit is added for generating invalid states, which are states contained in the generated test patterns but cannot be set by a normal transition from the reset state. A multiplexer is added for selecting the output of a next-state generation logic circuit or the invalid-state generation logic circuit for input to the state register based on a state transition mode selection signal. Signals corresponding to pseudo-primary outputs during test generation are made observable, and the multiplexer output signal is externally detectable as a state output signal.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: December 25, 2001
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hideo Fujiwara, Toshimitsu Masuzawa, Satoshi Ohtake