Patents by Inventor Toshimoto Kubota

Toshimoto Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7436118
    Abstract: A plasma display panel is disclosed. It can display quality videos and its manufacturing steps can be reduced. A pair of substrates (3), (11) confront each other to form dischargeable space (16) in between. At least front one (3) of the substrates is transparent, and includes display electrodes (6) formed of scan electrodes (4) and sustain electrodes (5), as well as light-blocking sections (7) corresponding to non-dischargeable sections (18) disposed between the display electrodes (6). The other substrate (11) facing to rear includes phosphor layers (15R), (15G), (15B) which emit light by discharging. Each one of display electrodes (6) is formed of transparent electrodes (4a), (5a) and bus electrodes (4b), (5b) which are formed of a plurality of electrode-layers. At least one of the electrode-layers is made of black layer (19) having a specific volume resistance ranging from 1×105 ?cm to 1×109 ?cm, and light-blocking sections (7) are made of identical material of black layer (19).
    Type: Grant
    Filed: November 25, 2004
    Date of Patent: October 14, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daisuke Adachi, Hiroyuki Yonehara, Toshimoto Kubota
  • Publication number: 20060145622
    Abstract: A plasma display panel is disclosed. It can display quality videos and its manufacturing steps can be reduced. A pair of substrates (3), (11) confront each other to form dischargeable space (16) in between. At least front one (3) of the substrates is transparent, and includes display electrodes (6) formed of scan electrodes (4) and sustain electrodes (5), as well as light-blocking sections (7) corresponding to non-dischargeable sections (18) disposed between the display electrodes (6). The other substrate (11) facing to rear includes phosphor layers (15R), (15G), (15B) which emit light by discharging. Each one of display electrodes (6) is formed of transparent electrodes (4a), (5a) and bus electrodes (4b), (5b) which are formed of a plurality of electrode-layers. At least one of the electrode-layers is made of black layer (19) having a specific volume resistance ranging from 1×105 ?cm to 1×109 ?cm, and light-blocking sections (7) are made of identical material of black layer (19).
    Type: Application
    Filed: November 25, 2004
    Publication date: July 6, 2006
    Inventors: Daisuke Adachi, Hiroyuki Yonehara, Toshimoto Kubota
  • Patent number: 6030869
    Abstract: A method for fabricating a nonvolatile semiconductor memory device having a stacked gate portion, including a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode, formed over a p-type Si substrate. In the p-type Si substrate, n.sup.++ source/drain layers and n.sup.+ source/drain layers, each layer containing arsenic, are formed. In the drain region, an n.sup.- drain layer, containing phosphorus and overlapping with an entire edge of the stacked gate portion in the gate width direction, and a p layer surrounding the bottoms of the n.sup.+ and the n.sup.- drain layers are provided. In such a structure, an electric field applied between the floating gate electrode and the drain is weakened and the drain-disturb characteristics are improved during writing.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: February 29, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinori Odake, Takashi Maejima, Hidenori Tanaka, Mitsuyoshi Andou, Toshimoto Kubota