Patents by Inventor Toshinari Sasaki

Toshinari Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250098321
    Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Applicant: Japan Display Inc.
    Inventors: Tatsuya TODA, Toshinari SASAKI, Masayoshi FUCHI
  • Publication number: 20250089302
    Abstract: A semiconductor device includes a metal oxide layer containing aluminum as a main component above an insulating surface, an oxide semiconductor layer on the metal oxide layer; a gate electrode facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a water contact angle on an upper surface of the metal oxide layer is 20° or lower.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Applicant: Japan Display Inc.
    Inventors: Takaya TAMARU, Masashi TSUBUKU, Hajime WATAKABE, Toshinari SASAKI
  • Publication number: 20250081617
    Abstract: A display device having a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels includes, a transistor including an oxide semiconductor layer, a gate wiring extending in the first direction opposite the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring, a first conductive layer provided on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer, a second insulating layer provided on the first conductive layer, a first inorganic layer provided on the second insulating layer and having openings therein, and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening.
    Type: Application
    Filed: August 28, 2024
    Publication date: March 6, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Akihiro HANADA, Takaya TAMARU, Marina MOCHIZUKI, Masahiro WATABE
  • Publication number: 20250081540
    Abstract: A thin film transistor includes an oxide semiconductor layer having a polycrystalline structure over a substrate, a gate electrode over the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a first region having a first carrier concentration and overlapping the gate electrode, a second region having a second carrier concentration and not overlapping the gate electrode, and a third region between the first region and the second region and overlapping the gate electrode. The second carrier concentration is larger than the first carrier concentration. A carrier concentration of the third region decreases from the second region to the first region in a channel length direction. A length of the third region is greater than or equal to 0.00 ?m and less than or equal to 0.60 ?m in the channel length direction.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicants: Japan Display Inc., IDEMITSU KOSAN CO., LTD.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Emi KAWASHIMA, Yuki TSURUMA, Daichi SASAKI
  • Publication number: 20250063751
    Abstract: A method for manufacturing a semiconductor device comprises steps of: forming an oxide semiconductor layer on a substrate by a sputtering method; performing a first heat treatment on the oxide semiconductor layer after placing the substrate on which the oxide semiconductor layer is formed in a heating furnace having a heating medium maintained at a preset temperature; forming a gate insulating layer on the oxide semiconductor layer after the first heat treatment; and forming a gate electrode on the gate insulating layer. When the substrate is installed in the heating furnace, a temperature drop of the heating medium is kept within 15% of the set temperature.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 20, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20250062121
    Abstract: An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (which is for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. Besides impurities such as moisture existing in the oxide semiconductor film, heat treatment causes reduction of impurities such as moisture existing in the gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor film and are in contact with the oxide semiconductor film.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 20, 2025
    Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
  • Publication number: 20250063761
    Abstract: A semiconductor device includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.
    Type: Application
    Filed: November 1, 2024
    Publication date: February 20, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Patent number: 12230715
    Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
    Type: Grant
    Filed: March 11, 2024
    Date of Patent: February 18, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshinari Sasaki, Katsuaki Tochibayashi, Shunpei Yamazaki
  • Patent number: 12230626
    Abstract: A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: February 18, 2025
    Assignee: Japan Display Inc.
    Inventor: Toshinari Sasaki
  • Publication number: 20250048680
    Abstract: A semiconductor device includes a substrate, an insulating layer over the substrate, a metal oxide layer over the insulating layer, and an oxide semiconductor layer over the metal oxide layer. The insulating layer includes a first region overlapping the metal oxide layer and a second region not overlapping the metal oxide layer. A hydrogen concentration of the first region is greater than a hydrogen concentration of the second region. A nitrogen concentration of the first region is greater than a nitrogen concentration of the second region.
    Type: Application
    Filed: September 27, 2024
    Publication date: February 6, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Patent number: 12213351
    Abstract: According to one embodiment, in a first concentration of an impurity element contained in a first impurity region, a second concentration of the impurity element contained in a second impurity region, a third concentration of the impurity element contained in a third impurity region, and a fourth concentration of the impurity element contained in a high-concentration impurity region, the third concentration is equal to the fourth concentration, the third concentration is higher than the first concentration, and the first concentration is higher than the second concentration.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: January 28, 2025
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akihiro Hanada, Toshinari Sasaki, Ryo Onodera
  • Patent number: 12206025
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: January 21, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Kengo Akimoto, Masashi Tsubuku, Toshinari Sasaki
  • Publication number: 20250022929
    Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer provided above an insulating surface, a gate insulating layer provided above the oxide semiconductor layer, and a gate electrode provided above the oxide semiconductor layer via the gate insulating layer, wherein the gate electrode has a titanium-containing layer and a conductive layer in order from the gate insulating layer side, the gate insulating layer includes a first region overlapping the gate electrode and a second region not overlapping the gate electrode, and a thickness of the titanium-containing layer is 50% or less than a thickness of the gate insulating layer in the first region.
    Type: Application
    Filed: September 26, 2024
    Publication date: January 16, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20250022964
    Abstract: A semiconductor device comprises a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a gate wiring on the gate insulating layer, and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. The first region overlaps the gate insulating layer and the gate wiring. The third region is in contact with the second insulating layer. A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer.
    Type: Application
    Filed: July 1, 2024
    Publication date: January 16, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Marina MOCHIZUKI, Ryo ONODERA, Masahiro WATABE
  • Publication number: 20250022966
    Abstract: A semiconductor device includes a metal oxide layer over an insulating surface and an oxide semiconductor layer over the metal oxide layer. A fluorine concentration of the metal oxide semiconductor layer is greater than or equal to 1×1018 atoms/cm3. In a SIMS analysis, a secondary ion intensity of fluorine detected in the metal oxide layer may be greater than or equal to 10 times a secondary ion intensity of fluorine detected in the oxide semiconductor layer.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU
  • Publication number: 20250022965
    Abstract: A semiconductor device according to an embodiment includes: a metal oxide layer above a substrate, the metal oxide layer containing aluminum as a main component; an oxide semiconductor layer above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein the oxide semiconductor layer includes two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Toshinari SASAKI, Hajime WATAKABE, Takaya TAMARU
  • Publication number: 20250015196
    Abstract: A thin film transistor includes a metal oxide layer over the substrate, an oxide semiconductor layer having crystallinity in contact with the metal oxide layer, a gate electrode overlapping the oxide semiconductor layer, and an insulating layer between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111> obtained by an EBSD method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation <001> is less than or equal to 5%.
    Type: Application
    Filed: September 19, 2024
    Publication date: January 9, 2025
    Applicants: Japan Display Inc., IDEMITSU KOSAN CO., LTD.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Emi KAWASHIMA, Yuki TSURUMA, Daichi SASAKI
  • Publication number: 20250015168
    Abstract: A method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component above an insulating surface; performing a planarization process on a surface of the first metal oxide layer; forming an oxide semiconductor layer on the insulating surface on which the planarization process is performed; forming a gate insulating layer above the oxide semiconductor layer; and forming a gate electrode facing the oxide semiconductor layer above the gate insulating layer.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Applicant: Japan Display Inc.
    Inventors: Takaya TAMARU, Masashi TSUBUKU, Hajime WATAKABE, Toshinari SASAKI
  • Publication number: 20250015198
    Abstract: An oxide semiconductor film having crystallinity over a substrate contains indium (In) and a first metal element (M1). The oxide semiconductor film includes a plurality of crystal grains. Each of the plurality of crystal grains includes at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111> obtained by an electron backscatter diffraction (EBSD) method. In occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate, an occupancy rate of the crystal orientation <111> is greater than an occupancy rate of the crystal orientation <001> and an occupancy rate of the crystal orientation <101>.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Applicants: Japan Display Inc., IDEMITSU KOSAN CO., LTD.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Emi KAWASHIMA, Yuki TSURUMA, Daichi SASAKI
  • Publication number: 20250015189
    Abstract: A semiconductor device includes a metal oxide layer over an insulating surface, an oxide semiconductor layer over the metal oxide layer, and an insulating layer over the oxide semiconductor. The insulating layer includes a first region overlapping the oxide semiconductor layer. A first aluminum concentration of the first region is greater than or equal to 1×1017 atoms/cm3.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU