Patents by Inventor Toshinari Takada

Toshinari Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5458763
    Abstract: A wiring pattern forming method in which side etch of a wiring pattern at the time of etching the substrate copper foil of a copper plating pattern is reduced to hold down an increase in line resistance, the wiring pattern forming method including the steps of: providing a plating resist pattern of which open area comprises a wiring pattern on the surface of a copper-clad laminate which is obtained by providing a copper foil on an insulating substrate; plating such open area with copper to form a copper plating pattern; then plating a crevice between the copper plating pattern and the plating resist pattern with a solder film by alternately repeating application of a current for a predetermined time period and suspension of the current application for a predetermined time period; and etching away the copper foil by using the solder film as an etching resist to form the wiring pattern.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: October 17, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shiro Kobayashi, Toshinari Takada, Haruo Akahoshi, Tomoyuki Miyazaki, Kanji Yamamoto
  • Patent number: 5294291
    Abstract: A process is provided for the formation of a conductive circuit pattern on a base metal formed on a substrate. On the base metal, a plating resist is first provided in a pattern corresponding to the circuit to be formed and a circuit pattern is then formed by plating. The plating resist is treated with a stripper and then with a stripping residue remover to cut off chemical bonds in the resist by a dehydrating decomposition reaction. The base metal is treated with an etchant for the base metal, whereby any resist residue still remaining after the treatment with the stripping residue remover is removed and the base metal are etched at areas which were covered by the plating resist.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: March 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Haruo Akahoshi, Toshinari Takada, Fujiko Yutani, Takeyuki Itabashi, Shin Nishimura, Satoru Amo, Akio Takahashi, Rituji Toba, Masashi Miyazaki
  • Patent number: 5249547
    Abstract: A manually operated sizing machine comprising a sheet roll unit, a size container with a sheet pullout port, a separation wall thereof and a clearance at the bottom of said wall, and designed to size a sheet pulled out through the clearance at the bottom of the separation wall.It is a compact and less expensive machine which permits easy and even sizing on wall paper, floor sheet and various kinds of sheet.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: October 5, 1993
    Assignee: Kyokutosanki Co., Ltd.
    Inventors: Toshinari Takada, Masatoshi Wakabayashi, Arata Koroyasu, Yasuaki Matsui
  • Patent number: 5230737
    Abstract: The wallpaper pasting apparatus characterized in that the wallpaper pasting apparatus is provided with a pasting roller and a pressing guide for pressing the wallpaper against the upper surface thereof, by a plurality of levelling plate means having edge wavy grooves for adjusting the thickness of the paste layer transferred onto the wallpaper.This apparatus has a simple structure and a light weight, and permits easy and accurate adjustment of the thickness of the paste layer.
    Type: Grant
    Filed: May 1, 1991
    Date of Patent: July 27, 1993
    Assignee: Kyokutosanki Co., Ltd.
    Inventors: Toshinari Takada, Yusuke Yokota, Arata Koroyasu, Yasuaki Matsui
  • Patent number: 5021296
    Abstract: A circuit board, which comprises an insulating substrate, a copper wiring having a coarsely roughened surface provided on the insulating substrate, and a copper oxide-reduced layer provided on the coarsely roughened surface of the copper wiring and formed by reduction of copper oxide and electroless plating, the copper oxide-reduced layer having a finely roughed surface and having a deposited layer of at least one of nickel and cobalt, where the copper oxide-reduced layer having a deposited layer of at least one of nickel and cobalt on the surface is roughened in a range of 0.05 to 5 .mu.m in terms of a maximum vertical distance between the top of convex parts and the bottom of concave parts of the copper oxide-reduced layer per .mu.m of the longitudinal distance of the copper oxide-reduced layer, and at least one of nickel and cobalt is deposited in an amount of 5.times.10.sup.-7 to 1.times.10.sup.-4 g/cm.sup.2 on the copper oxide-reduced layer, has a high adhesiveness to an insulating resin.
    Type: Grant
    Filed: September 18, 1989
    Date of Patent: June 4, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Suzuki, Toshinari Takada, Masahiro Suzuki, Haruo Akahoshi, Akira Nagai, Akio Takahashi, Shigeo Amagi, Toshikazu Narahara, Motoyo Wajima, Kiyonori Kogawa