Patents by Inventor Toshinori Araki
Toshinori Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12183118Abstract: Facial recognition adversarial patch adjustment is performed by applying a patch to a digital image including image data representing a face to obtain a patched image, applying a face detector to the patched image to obtain a detection value representing a likelihood that the patched image includes image data representing facial features, applying a feature extractor to the patched image to obtain a feature vector, applying a similarity determiner to the feature vector and a target feature vector to obtain a similarity value representing a likelihood that the patched image includes image data representing a target face, calculating a loss based on the detection value and the similarity value, and adjusting the patch based on the loss.Type: GrantFiled: November 25, 2021Date of Patent: December 31, 2024Assignee: NEC CorporationInventors: Inderjeet Singh, Toshinori Araki
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Patent number: 12147547Abstract: The information processing apparatus comprises a basic operation seed storage part, a reshare value computation part, and a share construction part. The basic operation seed storage part stores a seed for generating a random number used when computation is performed on a share. The reshare value computation part generates a random number using the seed, computes a share reshare value using the generated random number, and transmits data regarding the generated random number to other apparatuses. The share construction part constructs a share for type conversion using the data regarding the generated random number and the share reshare value received from other apparatuses.Type: GrantFiled: February 12, 2019Date of Patent: November 19, 2024Assignee: NEC CORPORATIONInventors: Hikaru Tsuchida, Toshinori Araki, Kazuma Ohara, Takuma Amada
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Publication number: 20240329590Abstract: An image forming system includes an image forming apparatus including an AC-DC converter and a main board, and a sub board having a sub connector connectable with a main connector of the main board. When the sub board is not connected with the main board, a main DC-DC converter on the main board converts a DC voltage from the AC-DC converter into a first DC voltage and output the first DC voltage to a circuit element for image formation. When the sub board is connected with the main board, the AC-DC converter outputs the DC voltage to a sub DC-DC converter on the sub board via the main connector and the sub connector, and the sub DC-DC converter converts the DC voltage from the AC-DC converter into a second DC voltage and output the second DC voltage to the circuit element via the sub connector and the main connector.Type: ApplicationFiled: March 28, 2024Publication date: October 3, 2024Applicant: BROTHER KOGYO KABUSHIKI KAISHAInventors: Yoshiyuki TSUJIMOTO, Nobuyuki TANAKA, Toshinori ARAKI, Seiya SATO, Shunsuke AIBA, Yutaro KUGE
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Patent number: 11991178Abstract: In a secret computation system, each of the three or more secret computation servers is configured to transmit, to the auxiliary server, carry computation information for computing a carry indicating whether or not digit carry occurs when a share of arithmetic operation is added as a binary number. The auxiliary server is configured to compute the carry based on the carry computation information received and compute an adjustment value used for computing the share of the arithmetic operation from a share of logical operation by using the computed carry. The auxiliary server distributes the computed adjustment value to the three or more secret computation servers. Each of the three or more secret computation servers is configured to convert the share of the logical operation to the share of the arithmetic operation by using a distributed value of the adjustment value.Type: GrantFiled: October 4, 2019Date of Patent: May 21, 2024Assignee: NEC CORPORATIONInventors: Hikaru Tsuchida, Toshinori Araki, Kazuma Ohara
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Publication number: 20240160946Abstract: A learning device for a neural network uses the base data group to update a parameter value of the partial network and a parameter value of the normalization layer associated with the entire base data group, and uses each group of adversarial examples of each adversarial example generation condition to update the parameter value of the partial network and the parameter value of the normalization layer associated with the condition. The neural network includes a partial network, a normalization layer associated with the entirety of a base data group including a plurality of data, and a normalization layer associated with each condition of adversarial example generation.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: NEC CorporationInventors: Toshinori ARAKI, Kazuya KAKIZAKI, Inderjeet SINGH
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Publication number: 20240160947Abstract: A learning device for a neural network uses a base data group, which is a group including a plurality of data, to update a parameter value of the partial network and a parameter value of the second normalization layer, and uses an adversarial example determined to induce an error in estimation using the neural network, among adversarial examples included in an adversarial data group, which is a group including a plurality of adversarial examples with respect to the data included in the base data group, to update the parameter value of the partial network and a parameter value of the first normalization layer. The neural network includes a partial network, a first normalization layer normalizing data input to the first normalization layer itself, and a second normalization layer normalizing data input to the second normalization layer itself.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Applicant: NEC CorporationInventors: Toshinori Araki, Kazuya Kakizaki, Inderjeet Singh
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Patent number: 11985232Abstract: There is provided a secure computing server that performs shift operation on secretly distributed shares. The secure computing server may perform the shift operation when a number of significant digits of secret information corresponding to a secretly distributed share is to be reduced.Type: GrantFiled: October 26, 2018Date of Patent: May 14, 2024Assignee: NEC CORPORATIONInventor: Toshinori Araki
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Patent number: 11934518Abstract: A verification apparatus acquires a source code for multiparty computation, while changing a combination of options settable to a multiparty computation compiler, compiles the source code for each combination of options to generate a plurality of multiparty computation executable codes, selects at least one multiparty computation executable code from the plurality of multiparty computation executable codes as a verification code and provides the at least one verification code to a verification environment of multiparty computation, generates an evaluation index with respect to an execution result of at least one verification code in the verification environment, and selects at least one recommended code from the plurality of multiparty computation executable codes, based on the evaluation index corresponding to at least one verification code and outputs the selected recommended code.Type: GrantFiled: January 9, 2019Date of Patent: March 19, 2024Assignee: NEC CORPORATIONInventors: Hikaru Tsuchida, Takao Takenouchi, Toshinori Araki, Kazuma Ohara, Takuma Amada
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Patent number: 11895230Abstract: An information processing apparatus comprises a partial modular exponentiation calculating part and a partial modular exponentiation synthesizing part. The partial modular exponentiation calculating part is given a base in plaintext and a modulo in plaintext and shared exponents and calculates a partial modular exponentiation that equals a set of shared values according to a modular exponentiation of the base raised by the shared exponent. The partial modular exponentiation synthesizing part calculates shared values of the modular exponentiation from the partial modular exponentiation that equals shared values relating to the modular exponentiation of a sum of shared exponents.Type: GrantFiled: January 24, 2019Date of Patent: February 6, 2024Assignee: NEC CORPORATIONInventors: Kazuma Ohara, Toshinori Araki
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Publication number: 20240027955Abstract: An image-forming apparatus includes: a main casing; a drawer movable in a first direction between a first position inside the main casing and a second position outside the main casing; process cartridges attachable to and detachable from the drawer; a controller; and a device-side terminal connected to the controller. The process cartridges are arranged in the first direction in an attached state to the drawer. Each process cartridge includes a photosensitive drum, a magnetic roller, a developing container for storing carrier, a conveying member, a toner sensor, a process memory, and a process-side terminal. The toner sensor is configured to output a detection signal corresponding to a concentration of toner in the developing container. The process-side terminal is for both outputting the detection signal of the toner sensor and outputting information about the process cartridge stored in the process memory. The device-side terminal is configured to contact the process-side terminal.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Applicant: BROTHER KOGYO KABUSHIKI KAISHAInventors: Shinta SUGIURA, Shunsuke AIBA, Keita INOUE, Kentaro AOYAMA, Toshinori ARAKI
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Patent number: 11870892Abstract: When an absolute value of a difference value between a first share and a second share which are secret-shared is less than or equal to a natural number t, the information processing apparatus calculates the difference value between the first share and the second share. Furthermore, the information processing apparatus performs a comparison in magnitude of the first share and the second share using bit-decomposition from a least significant bit to an m-th bit (m being a natural number) of the difference value.Type: GrantFiled: October 11, 2018Date of Patent: January 9, 2024Assignee: NEC CORPORATIONInventors: Hikaru Tsuchida, Toshinori Araki, Kazuma Ohara
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Patent number: 11762332Abstract: An image forming apparatus includes a main body, a drum cartridge removably attached to the main body, and a belt unit removably attached to the main body. The main body includes a drum power supply, a belt power supply, and a controller configured to start supplying power from the drum power supply to a drum memory of the drum cartridge, start supplying power from the belt power supply to a belt memory of the belt unit, stop supplying the power from the drum power supply to the drum memory after starting supplying the power from the drum power supply to the drum memory, and stop supplying the power from the belt power supply to the belt memory after starting supplying the power from the belt power supply to the belt memory.Type: GrantFiled: January 10, 2022Date of Patent: September 19, 2023Assignee: Brother Kogyo Kabushiki KaishaInventors: Toshinori Araki, Tatsuro Yokoi, Seiya Sato, Shinta Sugiura, Koji Akagi, Masaaki Wakizaka, Keita Inoue, Osamu Takahashi
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Publication number: 20230281964Abstract: Deep metric learning models are trained with multi-target adversarial examples by initializing a perturbation applied to a clean sample selected from a training sample set to form an adversarial example, the clean sample associated with a label sample, applying a deep metric learning model to the adversarial example and a plurality of target samples selected from the training sample set to obtain an adversarial feature vector and a plurality of target feature vectors, respectively, adjusting the perturbation to reduce difference among the adversarial feature vector and the plurality of target feature vectors to generate a multi-target adversarial example, applying the deep metric learning model to the clean sample, the label sample, and the multi-target adversarial example to obtain a clean feature vector, a label feature vector, and a multi-target adversarial feature vector, respectively, and adjusting the deep metric learning model based on the clean feature vector, the label feature vector, and the multi-tType: ApplicationFiled: March 4, 2022Publication date: September 7, 2023Inventors: Inderjeet SINGH, Kazuya KAKIZAKI, Toshinori ARAKI
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Publication number: 20230222782Abstract: An adversarial example detection device includes a first feature extraction unit configured to extract first features with respect to input data and comparative data in a first calculation method, a second feature extraction unit configured to extract second features with respect to the input data and the comparative data in a second calculation method different from the first calculation method, and a determination unit configured to determine whether or not at least one piece of the input data and the comparative data is an adversarial example through calculation using the first features and the second features.Type: ApplicationFiled: June 5, 2020Publication date: July 13, 2023Applicant: NEC CorporationInventors: Takuma AMADA, Kazuya KAKIZAKI, Toshinori ARAKI
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Patent number: 11619897Abstract: In an image forming apparatus, an image forming unit configured to form a toner image on a transfer medium includes four sets of a photoconductor drum and a development roller, respectively, for forming toner images of first, second, third and fourth colors, arranged in this order, in a direction opposite to a direction of movement of the transfer medium moving toward a detector configured to detect a toner image formed on the transfer medium. A controller executes a bias-corrective test image forming process in which a first bias-corrective test image of the first color is arranged in a position downstream of other three first bias-corrective test images, and a second bias-corrective test image of the first color is arranged in a position between two first bias-corrective test images selected among other three first bias-corrective test images, in the direction of movement of the transfer medium.Type: GrantFiled: June 3, 2022Date of Patent: April 4, 2023Assignee: BROTHER KOGYO KABUSHIKI KAISHAInventors: Miho Ishida, Shintaro Fukuoka, Toshio Furukawa, Toshinori Araki, Masaya Takasu, Takuro Nishimura
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Patent number: 11599681Abstract: The present invention provides a bit decomposition secure computation system comprising: a share value storage apparatus to store share values obtained by applying (2, 3) type RSS using modulo of power of 2 arithmetic; a decomposed share value storage apparatus to store a sequence of share values obtained by applying (2, 3) type RSS using modulo 2 arithmetic; and a bit decomposition secure computation apparatus that, with respect to sharing of a value w, r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over (?)}n, where {circumflex over (?)} is a power operator and n is a preset positive integer, being used as share information by the (2, 3) type RSS stored in the share value storage apparatus, includes: an addition sharing unit that sums two values out of r1, r2 and r3 by modulo 2{circumflex over (?)}n, generates and distributes a share value of the (2, 3) type RSS with respect to the sum; and a full adder secure computation unit that executes addition processing of the value generated by the addition sType: GrantFiled: May 18, 2017Date of Patent: March 7, 2023Assignees: NEC CORPORATION, BAR-ILAN UNIVERSITYInventors: Toshinori Araki, Kazuma Ohara, Jun Furukawa, Lindell Yehuda, Nof Ariel
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Publication number: 20220397852Abstract: In an image forming apparatus, an image forming unit configured to form a toner image on a transfer medium includes four sets of a photoconductor drum and a development roller, respectively, for forming toner images of first, second, third and fourth colors, arranged in this order, in a direction opposite to a direction of movement of the transfer medium moving toward a detector configured to detect a toner image formed on the transfer medium. A controller executes a bias-corrective test image forming process in which a first bias-corrective test image of the first color is arranged in a position downstream of other three first bias-corrective test images, and a second bias-corrective test image of the first color is arranged in a position between two first bias-corrective test images selected among other three first bias-corrective test images, in the direction of movement of the transfer medium.Type: ApplicationFiled: June 3, 2022Publication date: December 15, 2022Applicant: BROTHER KOGYO KABUSHIKI KAISHAInventors: Miho ISHIDA, Shintaro FUKUOKA, Toshio FURUKAWA, Toshinori ARAKI, Masaya TAKASU, Takuro NISHIMURA
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Publication number: 20220343027Abstract: A computation system according to the present disclosure includes: shuffling secure computation means for executing secure computation processing by shuffling; random bit sharing means for generating, as security parameters, K pieces of random data; and unauthorized action detecting secure computation means for determining that an exclusive OR operation of values for all rows obtained by multiplying the exclusive OR operation of each row of the tables before the shuffling processing for each data designated by the i-th random data by the i-th random bit of each row is the same as an exclusive OR operation of values for all rows obtained by multiplying the exclusive OR operation of each row of the tables after the shuffling processing for each data designated by the i-th random data by the i-th random bit of each row.Type: ApplicationFiled: September 26, 2019Publication date: October 27, 2022Applicants: NEC Corporation, BAR-ILAN UNIVERSITYInventors: Toshinori ARAKI, Kazuma OHARA, Hikaru TSUCHIDA, Jun FURUKAWA, Binyamin PINKAS
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Publication number: 20220335298Abstract: A robust learning device is a learning device that, with a parameter of n neural networks, training data, and a correct label serving as inputs, outputs the updated parameter, including: a model selection unit that selects neural networks, which are less than n and equal to or more than two, among the n neural networks; a limited objective function calculation unit that calculates, in a calculation process of an objective function including a process in which a value of the objective function becomes smaller as an output of the neural networks to the training data is closer to the correct label and a degree of similarity between the neural networks is smaller, a limited objective function including only the process relating to the neural networks selected by the model selection unit; and an update unit that updates the parameter such that a value of the limited objective function is decreased.Type: ApplicationFiled: October 1, 2019Publication date: October 20, 2022Applicant: NEC CorporationInventors: Takuma AMADA, Kazuya KAKIZAKI, Toshinori ARAKI
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Publication number: 20220329596Abstract: In a secret computation system, each of the three or more secret computation servers is configured to transmit, to the auxiliary server, carry computation information for computing a carry indicating whether or not digit carry occurs when a share of arithmetic operation is added as a binary number. The auxiliary server is configured to compute the carry based on the carry computation information received and compute an adjustment value used for computing the share of the arithmetic operation from a share of logical operation by using the computed carry. The auxiliary server distributes the computed adjustment value to the three or more secret computation servers. Each of the three or more secret computation servers is configured to convert the share of the logical operation to the share of the arithmetic operation by using a distributed value of the adjustment value.Type: ApplicationFiled: October 4, 2019Publication date: October 13, 2022Applicant: NEC CorporationInventors: Hikaru TSUCHIDA, Toshinori ARAKI, Kazuma OHARA