Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type, impurities.

Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type impurities.

Abstract: A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (MOSFET) region defined by a device isolation layer and having an active pattern extending in a first direction on the MOSFET region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the MOSFET region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the MOSFET region is a P-channel. MOSFET (PMOSFET) region. The first gate separation pattern has a compressive strain when the MOSFET region is an N-channel MOSFET (NMOSFET) region.

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied.

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied.

Abstract: A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detection circuit (50). The FET (20) is provided in a double well (40). M (m is a natural number) contact plugs (32) are connected to a diffusion layer (22) of the FET (20) while n (n is a natural number) contact plugs (34) are connected to a diffusion layer (24). Here, m is smaller than n. The detection circuit (50) detects the difference between the output of the FET (10) and the output of the FET (20).

Abstract: A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detection circuit (50). The FET (20) is provided in a double well (40). M (m is a natural number) contact plugs (32) are connected to a diffusion layer (22) of the FET (20) while n (n is a natural number) contact plugs (34) are connected to a diffusion layer (24). Here, m is smaller than n. The detection circuit (50) detects the difference between the output of the FET (10) and the output of the FET (20).

Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.

Abstract: Aiming at improving productivity of the semiconductor devices and at improving the product yield, a method of the present invention fabricates a semiconductor device by using, as a photomask, a first photomask 106 having a first rectangular pattern 104a obtained by dividing a mask pattern, and a second photomask 108 having a second rectangular pattern 104b obtained by dividing the mask pattern, wherein the method includes a first step processing a sacrificial film formed on a semiconductor substrate, using the first photomask 106 to thereby form therein a first rectangular pattern 104a; a second step processing the sacrificial film using the second photomask 108 to thereby form therein a second rectangular pattern 104b; and a third step etching the film formed on the semiconductor substrate, using, as a mask, the sacrificial film processed as having the rectangular pattern 104a and the second rectangular pattern 104b formed therein.

Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.

Abstract: An objective of this invention is to improve an ON-state current of a field-effect transistor. For this purpose, on a single-crystal silicon substrate 101 having a {100} plane as a principal surface are formed a gate electrode 107 extending substantially in a <010> crystal axis direction of the single-crystal silicon or an axis direction equivalent to the <010> crystal axis direction, and in both sides of the gate electrode 107, source/drain regions 129 on the surface of the single-crystal silicon substrate 101. On the surface of the single-crystal silicon substrate 101 in a region directly below the gate electrode 107 are formed a principal surface and an inclined surface 133 oblique to the principal surface along the extension direction of the gate electrode 107.