Patents by Inventor Toshinori Harada
Toshinori Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8038127Abstract: The object of the present invention is to provide a method for manufacturing hydrogen-added water containing a large amount of microscopic bubbles and manufacturing equipment for the same so as to expand the industrial applicability of hydrogen-added water by injecting a large amount of microscopic bubbles. More specifically, a plurality of tubular structures, in which the diffusion chamber (5), having double tubes, is provided, and a porous element (6) having predetermined pore diameters, in the diffusion chamber (5) is provided and are substantially linearly arranged in a longitudinal direction. The raw water and hydrogen are supplied with one of the tubular structures, so as to form the mixture of raw water and hydrogen by mixing supplied raw water and hydrogen in the diffusion chamber (5). The mixture is passed through the porous element (6) and diffused therein. The mixture fluid of raw water and hydrogen is then supplied to an adjacent tubular structure under high pressure.Type: GrantFiled: July 6, 2007Date of Patent: October 18, 2011Assignees: Hiroshima Kasei, Ltd., H4O Inc.Inventors: Daigo Matsuoka, Maiko Takebe, Takahiro Hayama, Toshinori Harada, Yuuichi Takagaki, Hisakazu Matsui
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Publication number: 20100219260Abstract: The object of the present invention is to provide a method for manufacturing the hydrogen-added water containing a large amount of the microscopic bubbles and a manufacturing equipment for the same so as to expand the industrial applicability of the hydrogen-added water by containing the large amount of the microscopic bubbles. More specifically, a plurality of tubular structures, in which the diffusion chamber 5 having the double tubes is provided, and the porous element 6 having predetermined pore diameters in the diffusion chamber 5 are provided, are substantially linearly arranged in a longitudinal direction. The raw water and the hydrogen are supplied with one of the tubular structures, so as to form the mixture fluid of the raw water and the hydrogen by mixing the supplied raw water and hydrogen in the diffusion chamber 5. The mixture fluid is passed through the porous element 6 and diffused therein.Type: ApplicationFiled: July 6, 2007Publication date: September 2, 2010Inventors: Daigo Matsuoka, Maiko Takebe, Takahiro Hayama, Toshinori Harada, Yuuichi Takagaki, Hisakazu Matsui
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Publication number: 20040228194Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: June 22, 2004Publication date: November 18, 2004Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6765840Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: February 4, 2003Date of Patent: July 20, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6711054Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: November 19, 2002Date of Patent: March 23, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Publication number: 20030128604Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: February 4, 2003Publication date: July 10, 2003Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6556499Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: February 6, 2002Date of Patent: April 29, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Publication number: 20030072202Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: ApplicationFiled: November 19, 2002Publication date: April 17, 2003Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6490195Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: October 1, 2001Date of Patent: December 3, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Publication number: 20020114183Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: February 6, 2002Publication date: August 22, 2002Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6385085Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: April 10, 2001Date of Patent: May 7, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Publication number: 20020008991Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: ApplicationFiled: October 1, 2001Publication date: January 24, 2002Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6301150Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: April 28, 2000Date of Patent: October 9, 2001Assignee: Hitachi, Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Publication number: 20010015909Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: April 10, 2001Publication date: August 23, 2001Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6222763Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: February 3, 2000Date of Patent: April 24, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6078519Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: May 25, 1999Date of Patent: June 20, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6026014Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: December 19, 1997Date of Patent: February 15, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto