Patents by Inventor Toshinori Hiraishi

Toshinori Hiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6745341
    Abstract: An information processing apparatus having a plurality of CPUs has increased reliability. When one of storage devices suffers a fault, a corresponding control device indicates the fault to other control devices, so that all the control devices can recognize the fault. When either one of the CPUs has accessed the storage device, the control device indicates the occurrence of the fault to the CPU. Upon reception of the indication of the occurrence of the fault, the CPU changes the storage device for an active system, if necessary, according to predetermined rules. The same processing is performed when other CPUs have accessed the storage device. As a result, when all the CPUs have accessed the storage device, the setting up of the active system is completed.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: June 1, 2004
    Assignee: Fujitsu Limited
    Inventors: Shinichi Onitsuka, Toshinori Hiraishi, Akihiko Hisada, Noriaki Shimizu, Noboru Izumi
  • Patent number: 6728746
    Abstract: A computer system includes at least one real machine provided with a machine controller and/or a plurality of virtual machines provided with a machine controller and an operating system for a virtual machine, the real machine and the plurality of virtual machines are connected to a shared memory.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: April 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Murase, Sunao Takahira, Toshinori Hiraishi, Masaru Saito, Kenichiro Shimogawa, Katsunori Hiraoka, Koshi Horizaki, Kenichi Tsukamoto, Yumi Ochiai
  • Patent number: 5737509
    Abstract: A method of restoring data coherency is disclosed, whereby a duplex shared memory subsystem quickly recovers from a failure of one of the duplexed memory pair. A cluster first divides the duplex shared memory subsystem into segments each of which is a unit for copying. After synchronizing itself with other operating clusters, the cluster initiates a coherency restoration process to be performed in cooperation with all other operating clusters, sharing the jobs related to the segments. This results in reducing the time required for the coherency restoration process where the system must operate in an unreliable, coherency-lacking situation.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: April 7, 1998
    Assignee: Fujitsu Limited
    Inventors: Masato Fushimi, Toshinori Hiraishi
  • Patent number: 5568609
    Abstract: A method is provided which controls a data processing system having two common memories forming a duplex memory, a plurality of clusters provided in common for the common memories, and input/output paths connecting the clusters to the common memories. The method includes the steps of detecting a failure which has occurred in one of the common memories by each of the clusters, physically disconnecting input/output paths connected to the above-mentioned one of the common memories therefrom when the failure is detected by one of the clusters, and inhibiting the clusters from accessing the above-mentioned one of the common memories in which the failure has occurred. There is also provided a data processing system that uses such a method.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: October 22, 1996
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Sugiyama, Toshinori Hiraishi, Tuyoshi Kumano
  • Patent number: 5548743
    Abstract: A method is provided which controls a data processing system having two common memories forming a duplex memory, a plurality of clusters provided in common for the common memories, and input/output paths connecting the clusters to the common memories. The method includes the steps of detecting a failure which has occurred in one of the common memories by each of the clusters, physically disconnecting input/output paths connected to the above-mentioned one of the common memories therefrom when the failure is detected by one of the clusters, and inhibiting the clusters from accessing the above-mentioned one of the common memories in which the failure has occurred. There is also provided a data processing system that uses such a method.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: August 20, 1996
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Sugiyama, Toshinori Hiraishi, Tuyoshi Kumano
  • Patent number: 5301311
    Abstract: A control method and system for preventing the incorrect resetting of a common resource in a multicomputer system comprising a plurality of clusters each having a processor and a common memory which each cluster can access. The method includes steps of storing in a common memory an IPL (initial Program Load) generation ID (Identifier) which is unique to an IPL number of each cluster, setting an acquisition ID and the IPL generation ID in the common resource, when the right to use the common resource in the common memory is acquired, and comparing the IPL generation ID when the faulty cluster stops, with the IPL generation ID set in the common resource, and only when the two IPL generation IDs are equal, resetting the right to use the common resource, when the right to use the common resource which the stopped faulty cluster acquires is reset.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: April 5, 1994
    Assignee: Fujitsu Limited
    Inventors: Masato Fushimi, Toshinori Hiraishi