Patents by Inventor Toshinori Hirashima
Toshinori Hirashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7160760Abstract: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer leads (37), (38) protruding in parallel from the same lateral surface of the resin encapsulant (29) and a header (28) bonded to a back surface of the semiconductor pellet and having a header protruding portion (28c) protruding from a lateral surface of the resin encapsulant (29) opposite to the lateral surface from which the outer leads protrude, wherein the header (28) has an exposed surface (28b) exposed from the resin encapsulant (29); the outer leads (37), (38) are bent; and the exposed of the outer leads (37), (38) are provided at substantially the same height.Type: GrantFiled: September 2, 2004Date of Patent: January 9, 2007Assignee: Renesas Technology Corp.Inventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Publication number: 20060197196Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: May 2, 2006Publication date: September 7, 2006Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20060197200Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: May 2, 2006Publication date: September 7, 2006Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 7089032Abstract: A radio transmitting/receiving device having at least three modules. The first module includes a first function for amplifying a radio frequency signal, demodulating the amplified radio frequency signal to a baseband signal and outputting the same, and a second function for modulating the input baseband signal, converting the modulated baseband signal to a radio frequency and outputting the same. The second module includes a function for amplifying the input radio frequency. The third module includes a function for executing a baseband signal process and controlling respective units according to a transmission/reception sequence based on a communication protocol.Type: GrantFiled: August 20, 2001Date of Patent: August 8, 2006Assignee: Renesas Technology CorporationInventors: Toyohiko Hongo, Toshinori Hirashima
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Publication number: 20050023671Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.Type: ApplicationFiled: September 2, 2004Publication date: February 3, 2005Inventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Publication number: 20040217474Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: May 28, 2004Publication date: November 4, 2004Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 6812554Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.Type: GrantFiled: October 7, 2002Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Patent number: 6774466Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: GrantFiled: January 28, 2000Date of Patent: August 10, 2004Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Publication number: 20040150082Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.Type: ApplicationFiled: January 16, 2004Publication date: August 5, 2004Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
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Patent number: 6740969Abstract: An electronic device having a first semiconductor device for powering MOSFET and a second semiconductor device for controlling on a principal surface and sealed by a resin body. The first semiconductor device has a semiconductor chip with a first and a second electrodes formed on a first principal surface and also with a third electrode formed on a second principal surface, and an insulative or dielectric sheet laid out between a first lead and the first principal surface of the semiconductor chip and between a second lead and the semiconductor ship for covering a specified area of the first principal surface of the semiconductor chip other than a region in which a plurality of projected electrodes are disposed. An upper surface of the first and second leads of the first semiconductor device is positioned under an upper surface of the resin body of the second semiconductor device in a thickness direction of a wiring substrate.Type: GrantFiled: September 13, 2000Date of Patent: May 25, 2004Assignee: Renesas Technology Corp.Inventor: Toshinori Hirashima
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Publication number: 20030143971Abstract: Principal components of a radio transmitting/receiving device are mounted in parts on three or four types of modules on each of which an interposer substrate (wiring board) is mounted wherein a pitch between terminals of semiconductor parts mounted on its main surface side is extended to a pitch between external terminals on its back side to connect between the terminals. On a first module, a function for amplifying a received radio frequency signal, demodulating the amplified radio frequency signal to a baseband signal and outputting the same, and a function for modulating the input baseband signal, converting the modulated baseband signal to a radio frequency and outputting the same are mounted. On a second module, a function for amplifying the input radio frequency to output power is mounted. On a third module, a function for executing a baseband signal process and controlling respective units according to a transmission/reception sequence based on a communication protocol is mounted.Type: ApplicationFiled: December 10, 2002Publication date: July 31, 2003Inventors: Toyohiko Hongo, Toshinori Hirashima
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Patent number: 6573119Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.Type: GrantFiled: July 12, 2001Date of Patent: June 3, 2003Assignee: Hitachi, Ltd.Inventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Patent number: 6569764Abstract: The semiconductor device includes a semiconductor chip having a first electrode and a second electrode formed on a first main surface and a third electrode formed on a second main surface opposite the first main surface. A first portion of a first lead is placed on the first electrode and a second portion of the first lead is located outside the semiconductor chip. A first portion of a second lead is placed on the second electrode and a second portion of the second lead is located outside the semiconductor chip. A plurality of projecting electrodes are provided between the first portion of the first lead and the first electrode and between the first portion of the second lead and the second electrode to electrically connect them. An insulating sheet is provided between the first portion of the first lead and the first main surface of the semiconductor chip and between the first portion of the second lead and the first main surface of the semiconductor chip.Type: GrantFiled: August 29, 2000Date of Patent: May 27, 2003Assignee: Hitachi, Ltd.Inventors: Toshinori Hirashima, Yasushi Takahashi, Ryoichi Kajiwara, Masahiro Koizumi, Munehisa Kishimoto
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Patent number: 6552421Abstract: The present invention provides a semiconductor device which is stably operated even with respect to heat generated upon its operation and makes no use of an environmental harmful substance (lead). The semiconductor device includes a support plate for supporting a semiconductor chip and the semiconductor chip fixed onto the support plate with an adhesive interposed therebetween. The semiconductor chip is fixed to the support plate by a highly thermal conductive adhesive and a high junction strength adhesive provided so as to separate bonding areas from one another. The highly thermal conductive adhesive is provided in plural places within the whole fixing area. The highly thermal conductive adhesive is associated with a heated portion of the semiconductor chip. The high junction strength adhesive is provided so as to surround the highly thermal conductive adhesive. Both the adhesives do not contain lead corresponding to the environmental harmful substance.Type: GrantFiled: May 31, 2001Date of Patent: April 22, 2003Assignee: Hitachi, Ltd.Inventors: Munehisa Kishimoto, Toshinori Hirashima, Hiroshi Satou, Hiroi Oka
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Publication number: 20030038360Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.Type: ApplicationFiled: October 7, 2002Publication date: February 27, 2003Inventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Patent number: 6479327Abstract: A package is disclosed in which deterioration of insulating encapsulation resin attributable to the generation of heat at source wires caused by an increase in a drain current is prevented. Specifically, there is provided a semiconductor package including a header made of metal, a semiconductor chip forming a power MOSFET secured on the header, an encapsulation element made of insulating resin covering the semiconductor chip, header and the like, a suspended lead contiguous with the header protruding from one side surface of the encapsulation element, a source lead and a gate lead protruding in parallel from one side surface of the encapsulation element, and wires positioned in the encapsulation element for connecting electrodes on the upper surface of the semiconductor chip and the source and gate leads. The source lead is constituted by a plurality of leads in parallel with each other, and the ends of the leads are coupled into one coupling portion in the encapsulation element.Type: GrantFiled: March 21, 2001Date of Patent: November 12, 2002Assignee: Hitachi, Ltd.Inventors: Yasushi Takahashi, Toshinori Hirashima
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Patent number: 6479888Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.Type: GrantFiled: February 11, 2000Date of Patent: November 12, 2002Assignee: Hitachi, Ltd.Inventors: Toshinori Hirashima, Munehisa Kishimoto, Toshiyuki Hata, Yasushi Takahashi
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Patent number: 6400019Abstract: The junction strength between the external terminals and the wiring substrate of a semiconductor device is improved without creating a large size semiconductor device. In the outer periphery of the back surface of an interposer substrate 1Bi on which a semiconductor chip constructing a CSP type semiconductor device 1 is mounted, there are arranged a plurality of bump electrodes 1BB1 whose size in the direction intersecting the sides of the interposer substrate 1B1 is larger than that in the direction along the sides of the interposer substrate 1Bi.Type: GrantFiled: November 9, 2000Date of Patent: June 4, 2002Assignee: Hitachi, Ltd.Inventors: Toshinori Hirashima, Yasushi Takahashi, Kenji Hanada, Takao Sonobe
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Patent number: 6335566Abstract: Disclosed herein is a semiconductor device in which a main surface of a semiconductor chip is placed over a first main surface of a wiring board so as to be opposed thereto and which includes a plurality of external terminals provided over a second main surface of the wiring board. The plurality of external terminals have a plurality of signal terminals and a plurality of power terminals. The signal terminals are arranged along the periphery of the wiring board and the power terminals are arranged along the inside of a row of the signal terminals. Chip capacitors are placed over the main surface of the semiconductor chip, which lies inside a row of the power terminals. The plurality of signal terminals and power terminals formed over the main surface of the semiconductor chip are connected to a plurality of wires formed over the wiring board respectively. The wiring board is provided with an opening or recess which extends therethrough. The chip capacitors are located within the opening or recess.Type: GrantFiled: November 30, 2000Date of Patent: January 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Toshinori Hirashima, Takefumi Endo, Kazuo Watanabe, Kenji Hanada, Takao Sonobe
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Publication number: 20010050422Abstract: The present invention provides a semiconductor device which is stably operated even with respect to heat generated upon its operation and makes no use of an environmental harmful substance (lead). The semiconductor device includes a support plate for supporting a semiconductor chip and the semiconductor chip fixed onto the support plate with an adhesive interposed therebetween. The semiconductor chip is fixed to the support plate by a highly thermal conductive adhesive and a high junction strength adhesive provided so as to separate bonding areas from one another. The highly thermal conductive adhesive is provided in plural places within the whole fixing area. The highly thermal conductive adhesive is associated with a heated portion of the semiconductor chip. The high junction strength adhesive is provided so as to surround the highly thermal conductive adhesive. Both the adhesives do not contain lead corresponding to the environmental harmful substance.Type: ApplicationFiled: May 31, 2001Publication date: December 13, 2001Inventors: Munehisa Kishimoto, Toshinori Hirashima, Hiroshi Satou, Hiroi Oka