Patents by Inventor Toshinori Hosokawa

Toshinori Hosokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7437340
    Abstract: The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: October 14, 2008
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
  • Patent number: 6708315
    Abstract: A design for testability is applied so as to enable significant reduction in test time of an actual integrated circuit. First, an integrated circuit is full-scan designed on a block-by-block basis and test input patterns are generated (S11). Then, one of the blocks to which the design for testability has not been allocated is selected (S12), and a full-scan design is allocated thereto (S14). Test points are inserted into a block that has more than a prescribed number of parallel test input patterns when that block is full-scan designed (YES in S15) (S16).
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Masayoshi Yoshimura
  • Patent number: 6651206
    Abstract: Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop, and the structure of the integrated circuit is checked if it has an n-folded line-up structure and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: November 18, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Mitsuyasu Ohta
  • Publication number: 20030188239
    Abstract: In a strongly testable DFT method, the length of a test sequence is reduced, thereby reducing the amount of circuitry to be added for testing purposes. Test plans, generated one for each of circuit elements forming a data path, are scheduled in parallel in a form that can be compacted, and a compaction operation is applied to generate a compacted test plan. The test sequence is generated by inserting the test patterns needed for each circuit element into the compacted test plan.
    Type: Application
    Filed: July 29, 2002
    Publication date: October 2, 2003
    Inventors: Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
  • Publication number: 20030097347
    Abstract: The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.
    Type: Application
    Filed: July 5, 2002
    Publication date: May 22, 2003
    Inventors: Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
  • Patent number: 6510535
    Abstract: A method of design for testability using scan FF identification of this invention eases generation of test sequences as compared with conventional technique. An FF relation graph is generated from an integrated circuit, FFs having self loops are recognized in the FF relation graph, and all FFs are replaced with scan FFs. FFs not having self loops are sorted in accordance with a predetermined evaluation function indicating the degree of relation with difficulty in generating test sequences. For example, a function indicating the degree of relation with a balanced reconvergence structure is used as the evaluation function. In a sort order thus obtained, with regard to each FF not having self loops, it is determined whether or not the integrated circuit has an n-fold line-up structure in assuming the FF is replaced with a non-scan FF, thereby identifying scan FFs.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: January 21, 2003
    Assignee: Matsushita Electric Industrial Co., Inc.
    Inventors: Toshinori Hosokawa, Toshihiro Hiraoka
  • Publication number: 20030009716
    Abstract: A method of design for testability using scan FF identification of this invention eases generation of test sequences as compared with conventional technique. An FF relation graph is generated from an integrated circuit, FFs having self loops are recognized in the FF relation graph, and all FFs are replaced with scan FFs. FFs not having self loops are sorted in accordance with a predetermined evaluation function indicating the degree of relation with difficulty in generating test sequences. For example, a function indicating the degree of relation with a balanced reconvergence structure is used as the evaluation function. In a sort order thus obtained, with regard to each FF not having self loops, it is determined whether or not the integrated circuit has an n-fold line-up structure in assuming the FF is replaced with a non-scan FF, thereby identifying scan FFs.
    Type: Application
    Filed: September 11, 2002
    Publication date: January 9, 2003
    Inventors: Toshinori Hosokawa, Toshihiro Hiraoka
  • Publication number: 20020129322
    Abstract: A design for testability is applied so as to enable significant reduction in test time of an actual integrated circuit. First, an integrated circuit is full-scan designed on a block-by-block basis and test input patterns are generated (S11). Then, one of the blocks to which the design for testability has not been allocated is selected (S12), and a full-scan design is allocated thereto (S14). Test points are inserted into a block that has more than a prescribed number of parallel test input patterns when that block is full-scan designed (YES in S15) (S16).
    Type: Application
    Filed: February 22, 2001
    Publication date: September 12, 2002
    Inventors: Toshinori Hosokawa, Masayoshi Yoshimura
  • Patent number: 6449743
    Abstract: Test sequences for use in fault testing for an integrated circuit are efficiently generated. The integrated circuit is subjected to timeframe expansion, thereby generating a time expansion model including a combinational circuit. With respect to this time expansion model, a compaction template is generated by compacting one or more primitive templates indicating whether or not a primary input or a pseudo primary input is present in each time. Test patterns are generated with respect to the time expansion model, and the generated test patterns are transformed, with compaction accompanied, into test sequences. The compaction is conducted by substituting the respective test patterns in the compaction template and connecting the resultant compaction templates. In this manner, short test sequences can be efficiently generated without spending much time on the compaction.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: September 10, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinori Hosokawa
  • Publication number: 20020026611
    Abstract: Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs. Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop, and the structure of the integrated circuit is checked if it has an-fold line-up structure, and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs. For example, timeframe expansion on the basis of the state justification of load/hold FFs is carried out.
    Type: Application
    Filed: March 27, 2001
    Publication date: February 28, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Mitsuyasu Ohta
  • Patent number: 6292915
    Abstract: The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL circuit which is designed to be easily testable by the method of design for testability. In the RTL circuit, scannable registers are selected so that the RTL circuit can attain an easily testable circuit structure such as an acyclic structure. This RTL circuit is timeframe expanded on the basis of a predetermined evaluation function and logically synthesized, so as to generate a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit, as a circuit for test sequence generation.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: September 18, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Tomoo Inoue, Hideo Fujiwara
  • Patent number: 6271677
    Abstract: A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: August 7, 2001
    Assignee: Matsushita Electric Industrial Company, Limited
    Inventors: Mitsuyasu Ohta, Toshinori Hosokawa, Sadami Takeoka, Osamu Ichikawa
  • Patent number: 6253343
    Abstract: Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs. Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop, and the structure of the integrated circuit is checked if it has an n-folded line-up structure and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: June 26, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Mitsuyasu Ohta
  • Patent number: 6185721
    Abstract: The invention provides a method of design for testability in which design of an integrated circuit is modified, at a register transfer level (RTL) with high abstraction than the gate level, so as to be simply testable and in which the area of a test circuit and the number of test patterns can be decreased as compared with those in the conventional method. An integrated circuit which has been designed in an RTL design step is partitioned into blocks each satisfying a previously defined simply testable condition in a partitioning step, so that the integrated circuit can be simply tested after manufacture. The simply testable condition can be that a circuit has an acyclic structure including no feedback loop, that a circuit has an n-fold line-up structure (wherein n is a positive integer), or the like.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: February 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinori Hosokawa
  • Patent number: 6016564
    Abstract: The invention provides a method of design for testability of a fault in a portion difficult to test such as an enable input of a tristate element. With regard to an integrated circuit design by a scan path method, an observation circuit including an EXOR tree having inputs in the number equal to that of tristate elements to be designed for testability and an observation dedicated scan FF is disposed. The enable inputs of the tristate elements are connected with the input terminals of the EXOR tree, and the output terminal of the EXOR tree is connected with the ordinary data input terminal of the observation dedicated scan FF. Furthermore, the observation scan FF is inserted into a scan chain already formed by the scan path method. In this manner, a fault in logic circuits for controlling the enable input of the tristate elements, which are conventionally difficult to be detected, can be observed at an external output pin through the scan chain.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinori Hosokawa
  • Patent number: 5748646
    Abstract: There is provided a design-for-testability method for path delay faults capable of assuring high fault coverage without any substantial increase in area overhead. In a given integrated circuit, an initial pattern is generated for the path delay fault selected, and logical values set for scan flip-flops in the initial pattern are stored. A transition pattern is generated for the selected path delay fault. It is judged whether or not the integrated circuit contains a scan flip-flop of which logical value set in the initial pattern is contradictory to the logical value set in the transition pattern. In the affirmative, a value holding element, for example a D latch, having a function of once holding an input data, is inserted in the output signal line of the scan flip-flop presenting a contradiction in logical value. This D latch eliminates a contradiction in logical value in the initial and transition patterns, thereby to prevent the generation of a test pattern from meeting with failure.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: May 5, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinori Hosokawa
  • Patent number: 5737341
    Abstract: In a method of generating a test sequence for testing a stuck-at fault supposed in a sequential circuit as a test circuit, the number of flip-flops which can be replaced with scan flip-flops among flip-flops included in the circuit under test is initially specified in the first step. Next, in the second step, there is calculated, for each of the flip-flops included in the circuit under test, the sequential depth of a clock defined as the minimum number of flip-flops that are passed through while the input side from the clock input terminal of the flip-flop is traced until an external input pin is reached. In the third step, flip-flops are identified with scan flip-flops by the number specified in the first step in the order of decreasing sequential depth of a clock, which was calculated in the second step.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: April 7, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinori Hosokawa
  • Patent number: 5483543
    Abstract: A method for generating a test sequence for a fault in a sequential circuit to provide high fault coverage. In one embodiment (FIG. 1), a circuit state, which a system fails to justify, is stored as an illegal state in a step 107. In a step 103, a target fault is selected. In a step 104, the system performs its fault propagation processing to generate a test sequence and propagate the target fault from a fault location to any external output pin in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. In a step 105, the system performs its state initialization processing to generate a test sequence and transfer the state of the circuit from its initial state to a state when the fault was sensitized in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation.
    Type: Grant
    Filed: September 23, 1992
    Date of Patent: January 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Akira Motohara, Mitsuyasu Ohta
  • Patent number: 5319647
    Abstract: An apparatus for and method of performing automatic test pattern generation for a digital circuit specified registers when the process of automatic test pattern generation for one or more faults is aborted which allow detection of circuit faults by scanning the specified registers. The scan request count of the specified registers is updated, and registers having a scan request count greater than the scan request count limit are recognized as critical registers. Automatic test pattern generation is performed while regarding the critical registers as scan registers.
    Type: Grant
    Filed: July 11, 1990
    Date of Patent: June 7, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Akira Motohara
  • Patent number: 5305328
    Abstract: An efficient method of generating test sequences for sequential circuits is disclosed. This method generates a test sequence for a combinational circuit which includes an object fault, examines memory elements where a resulting state (other than "don't care") has been set as a result of the fault. This is followed by fault propagation and state justification. In the event that, due to such factors as limitations in computing time, generation of test sequence was aborted during fault propagation or state justification, the states of the memory elements are provided for determining which memory element should be scanned to detect the fault. In another embodiment an assumed fault from previous processing has been propagated to a memory element and, thus, to a pseudo primary input terminal. The results of the previous processing are used to propagate the fault to a primary output terminal or to another memory element and, thus, to another pseudo primary output terminal.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: April 19, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Motohara, Toshinori Hosokawa, Mitsuyasu Ohta