Abstract: A built-in self-test circuit including a signal generator and operational elements. The operational elements perform arithmetic operations on a test signal value A, generated by the signal generator, to obtain a comparison signal value A which is fundamentally equal to the test signal value A of the signal generator. By comparing the test signal value A with the comparison signal value A, a test result is obtained.

Abstract: A semiconductor integrated circuit device includes a control circuit for coping with time differences in signals propagating along by differences in routes of the circuit device. In a definite data interval when changes of all signals have been completed, the control circuit outputs a received signal. In an indefinite data interval when changes of all signals have not been completed, the control circuit outputs a fixed signal irrespective of signal level of a received signal. The control circuit thus prevents irregular signal changes caused by the time differences before definition of data to subsequent circuits.

Abstract: The semiconductor integrated device includes a control circuit disposed to cope with time difference caused in changes of a plurality of signals by difference in routes. In a definite data interval when changes of all signals have been completed, the control circuit outputs a received signal. In an indefinite data interval when changes of all signals have not been completed, the control circuit outputs a fixed signal irrespective of a signal level of a received signal. The control circuit thus prevents irregular signal changes caused by the time difference before definition of data from being prevented to subsequent circuits.

Abstract: There is constituted a logic circuit verification apparatus designed for checking a semiconductor integrated circuit including a core and a new circuit. The core has a internal circuit in which logic and timing have already been verified. The apparatus is provided with a section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit. The apparatus is also provided with a section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit. At the time of simulation, predetermined processing is performed solely with regard to the extracted cells.

Abstract: A logic verification apparatus for a semiconductor integrated circuit classifies a program described in HDL into connection information of a synchronous circuit portion and connection information of a asynchronous circuit portion, converts a portion of the connection information of the asynchronous circuit portion into the connection information of the synchronous circuit portion and increases circuit portions the function of which can be verified by a cycle based simulation/static timing verification unit, thus making it possible to shorten the time for verification.

Abstract: A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.