Patents by Inventor Toshinori Koyama

Toshinori Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9820391
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 14, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Shoji Watanabe, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9620446
    Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 11, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Hiromu Arisaka, Akio Rokugawa, Toshinori Koyama
  • Patent number: 9520352
    Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 13, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9455219
    Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 27, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa, Toshinori Koyama
  • Patent number: 9380707
    Abstract: A method of manufacturing a wiring substrate includes: preparing a laminated plate of a metal layer and an insulating layer; adhering the laminated plate to a first support body facing the metal layer; and forming a first wiring layer with vias extending through the insulating layer and first pads exposed from a first surface of the insulating layer. The method also includes: separating a multilayer structure including the metal, insulating, and first wiring layer from the first support body; adhering the multilayer structure to a second support body facing the first wiring layer; removing the metal layer; forming a plurality of second wiring layers including second pads connected to the vias and exposed from a second surface of the insulating layer opposite the first surface; and separating the insulating, the first wiring, and the plurality of second wiring layers from the second support body, to obtain the wiring substrate.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: June 28, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Toshinori Koyama, Wataru Kaneda
  • Publication number: 20160172287
    Abstract: A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating layer is formed with through holes. The first via wirings are formed in the through holes. The connection terminals are electrically connected to the first wiring layer through the first via wirings. The connection terminals protrude upward from the first insulating layer. The protection layer is made of insulating resin which contains photosensitive resin as a main component. The protection layer is formed on an upper surface of the first insulating layer. The protection layer includes first and second protection layers. The first protection layer surrounds the connection terminals. The second protection layer is separated from the first protection layer. The second protection layer is thinner than the first protection layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 16, 2016
    Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Publication number: 20160174379
    Abstract: A wiring board includes plural terminals, an insulating layer, and recess portions. Each terminal includes a roughened upper surface and a roughened side surface. The insulating layer is formed between the terminals. The upper surfaces of the terminals are exposed. An upper surface of the insulating layer is a concave curved surface. The recess portions are formed in the insulating layer around the terminals so as to partially expose the side surfaces of the terminals.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 16, 2016
    Inventors: Noriyoshi Shimizu, Hiromu Arisaka, Akio Rokugawa, Toshinori Koyama
  • Patent number: 9220167
    Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 22, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Masato Tanaka, Toshinori Koyama, Akio Rokugawa
  • Patent number: 9167692
    Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Publication number: 20150282307
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 1, 2015
    Inventors: Noriyoshi SHIMIZU, Shoji WATANABE, Toshinori KOYAMA, Akio ROKUGAWA
  • Publication number: 20150245473
    Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.
    Type: Application
    Filed: February 17, 2015
    Publication date: August 27, 2015
    Inventors: Noriyoshi SHIMIZU, Masato TANAKA, Toshinori KOYAMA, Akio ROKUGAWA
  • Publication number: 20150001738
    Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Inventors: Noriyoshi SHIMIZU, Toshinori KOYAMA, Akio ROKUGAWA
  • Publication number: 20140225275
    Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.
    Type: Application
    Filed: December 27, 2013
    Publication date: August 14, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi SHIMIZU, Wataru KANEDA, Akio ROKUGAWA, Toshinori KOYAMA
  • Publication number: 20140150258
    Abstract: A wiring substrate includes a core portion and a wiring portion. The core portion includes a wiring layer and an organic resin core substrate. The wiring portion includes wiring layers and organic resin insulative layers. The wiring layer of the core portion is formed in a state in which the organic resin core substrate is supported by a support body. The wiring layers of the wiring portion are formed in a state in which the organic resin core substrate is adhered to a support body and the wiring layer of the core portion faces toward the support body.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 5, 2014
    Inventors: Noriyoshi SHIMIZU, Akio ROKUGAWA, Toshinori KOYAMA, Wataru KANEDA
  • Patent number: 7964950
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: June 21, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Patent number: 7691673
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 6, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Publication number: 20090206471
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Application
    Filed: April 21, 2009
    Publication date: August 20, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Patent number: 7573135
    Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: August 11, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Toshinori Koyama
  • Patent number: 7545049
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: June 9, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Patent number: 7498200
    Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 3, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Toshinori Koyama