Patents by Inventor Toshinori Morihara
Toshinori Morihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040219748Abstract: A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.Type: ApplicationFiled: May 27, 2004Publication date: November 4, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Masahiro Shimizu, Takashi Miyajima, Toshinori Morihara
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Patent number: 6756267Abstract: A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.Type: GrantFiled: November 25, 2002Date of Patent: June 29, 2004Assignee: Renesas Technology, Inc.Inventors: Masahiro Shimizu, Takashi Miyajima, Toshinori Morihara
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Patent number: 6635538Abstract: When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an electric field concentration in a pn junction, to effectively take advantage of an LDD structure. Since a portion of the insulating film (9) extending off the sidewalls (10) is removed, there is no need for etching of the insulating film (9) when the contact holes (12) are formed and only an insulating film (11) is etched. That prevents a short circuit between main electrodes (13) and a gate electrode (7) and makes it possible to determine the spacing between the contact holes (12) narrower than the width of the gate electrode (7).Type: GrantFiled: May 30, 2001Date of Patent: October 21, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinori Morihara, Yoshinori Tanaka
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Patent number: 6597599Abstract: In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.Type: GrantFiled: July 5, 2002Date of Patent: July 22, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinori Morihara, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
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Publication number: 20030077861Abstract: A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.Type: ApplicationFiled: November 25, 2002Publication date: April 24, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Masahiro Shimizu, Takashi Miyajima, Toshinori Morihara
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Patent number: 6541807Abstract: A storage node electrically connected to one of source/drain regions of a MOS transistor is formed along the side wall and the bottom wall of an opening provided through a silicon nitride film, a BPTEOS film and a TEOS film. The surface of this storage node is roughened. Thus, a semiconductor device having high reliability and a method of manufacturing the same are obtained.Type: GrantFiled: November 7, 2000Date of Patent: April 1, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshinori Morihara
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Publication number: 20030021140Abstract: In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffused area of the MOS transistor, the width W1 of the active region of the MOS transistor of field pattern FL constituting the memory cell is formed narrower than the width W2 of the active region of the capacitor.Type: ApplicationFiled: July 5, 2002Publication date: January 30, 2003Inventors: Toshinori Morihara, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
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Publication number: 20020195669Abstract: There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zoType: ApplicationFiled: August 16, 2002Publication date: December 26, 2002Inventors: Toshinori Morihara, Hiroki Shimano, Kazutami Arimoto
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Patent number: 6495418Abstract: A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.Type: GrantFiled: January 5, 2001Date of Patent: December 17, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Shimizu, Takashi Miyajima, Toshinori Morihara
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Patent number: 6487105Abstract: There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.Type: GrantFiled: December 22, 2000Date of Patent: November 26, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinori Morihara, Hiroki Shimano
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Patent number: 6459113Abstract: There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zoType: GrantFiled: January 17, 2001Date of Patent: October 1, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinori Morihara, Hiroki Shimano, Kazutami Arimoto
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Patent number: 6377483Abstract: Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.Type: GrantFiled: January 26, 2001Date of Patent: April 23, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazutami Arimoto, Hiroki Shimano, Toshinori Morihara
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Publication number: 20020031006Abstract: Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.Type: ApplicationFiled: January 26, 2001Publication date: March 14, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kazutami Arimoto, Hiroki Shimano, Toshinori Morihara
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Publication number: 20020028550Abstract: There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zoType: ApplicationFiled: January 17, 2001Publication date: March 7, 2002Inventors: Toshinori Morihara, Hiroki Shimano, Kazutami Arimoto
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Publication number: 20020019089Abstract: A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.Type: ApplicationFiled: January 5, 2001Publication date: February 14, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Shimizu, Takashi Miyajima, Toshinori Morihara
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Publication number: 20010055219Abstract: There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.Type: ApplicationFiled: December 22, 2000Publication date: December 27, 2001Inventors: Toshinori Morihara, Hiroki Shimano
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Patent number: 6271564Abstract: When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an electric field concentration in a pn junction, to effectively take advantage of an LDD structure. Since a portion of the insulating film (9) extending off the sidewalls (10) is removed, there is no need for etching of the insulating film (9) when the contact holes (12) are formed and only an insulating film (11) is etched. That prevents a short circuit between main electrodes (13) and a gate electrode (7) and makes it possible to determine the spacing between the contact holes (12) narrower than the width of the gate electrode (7).Type: GrantFiled: May 4, 1999Date of Patent: August 7, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinori Morihara, Yoshinori Tanaka
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Patent number: 5888854Abstract: A dielectric layer is formed on a main surface of a semiconductor substrate. A silicon layer is formed on dielectric layer. MOS transistors are formed in silicon layer and include impurity regions in a semiconductor layer. A capacitor is formed by cooperation of the impurity region, the dielectric layer, and the semiconductor substrate. The dielectric layer also serves as an insulating film of an SOI structure. Thus, a semiconductor memory device which achieves high performance and allows high integration can easily be obtained in a DRAM having an SOI structure.Type: GrantFiled: December 13, 1995Date of Patent: March 30, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshinori Morihara
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Patent number: 5495439Abstract: A dielectric layer is formed on a main surface of a semiconductor substrate. A silicon layer is formed on dielectric layer. MOS transistors are formed in the silicon layer and include impurity regions in a semiconductor layer. A capacitor is formed by cooperation of the impurity region, the dielectric layer, and the semiconductor substrate. The dielectric layer also serves as an insulating film of an SOI structure. Thus, a semiconductor memory device which achieves high performance and allows high integration can easily be obtained in a DRAM having an SOI structure.Type: GrantFiled: September 7, 1994Date of Patent: February 27, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshinori Morihara
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Patent number: 5404038Abstract: A semiconductor device and a method of manufacturing thereof has an opening of circular or oval columnar configuration in an active layer where a gate electrode is formed in self-alignment in a sidewall-spacer manner. The channel region has a curved surface so that a relatively large area can be ensured where the width of a gate electrode is constant to suppress the increase of threshold voltage due to narrow channel effect in accordance with miniaturization. Therefore, a vertical type MOS field effect transistor can be formed without degradation in transistor characteristic in accordance with miniaturization.Type: GrantFiled: April 28, 1992Date of Patent: April 4, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Toshinori Morihara