Abstract: A motion detector for a chrominance signal which is used with a TV receiver equipped with a video signal motion detector. This motion detector for a chrominance signal has a delay element for delaying the chrominance signal of a video signal by 1 frame period, a subtracter for subtracting the output signal of the delay element from the input signal thereof, an absolute value conversion circuit to which the output signal from the subtracter is inputted, and a smoother circuit to which the output signal from the absolute value conversion circuit is supplied. If the chrominance signal of video signals on two consecutive frames are the same, the output signal of the subtracter becomes zero. If the chrominance signals of video signals on two consecutive frames are different, the output signal of the subtracter takes a positive or negative value. The negative value signal is converted into a positive value signal by the absolute value conversion circuit.

Abstract: A motion detector for a chrominance signal which is used with a TV receiver equipped with a video signal motion detector. This motion detector for a chrominance signal has a delay element for delaying the chrominance signal of a video signal by 1 frame period, a subtractor for subtracting the output signal of the delay element from the input signal thereof, an absolute value conversion circuit to which the output signal from the subtractor is inputted, and a smoother circuit to which the output signal from the absolute value conversion circuit is supplied. If the chrominance signals of video signals on two consecutive frames are the same, the output signal of the subtractor becomes zero. If the chrominance signals of video signals on two consecutive frames are different, the output signal of the substractor takes a positive or negative value. The negative value signal is converted into a positive value signal by the absolute value conversion circuit.

Abstract: A circuit for separating a luminance signal and a chrominance signal having the first, second, third, and fourth 1H delay lines each connected in series, a first comb filter including the first and second 1H delay lines, a second comb filter including the second and third 1H delay lines, a third comb filter including the third and fourth 1H delay lines, a first subtraction circuit for achieving a subtraction on an input signal to the first 1H delay line and an output signal from the second 1H delay line, a second subtraction circuit for achieving a subtraction on an input signal to the second 1H delay line and an output signal from the third 1H delay line, a third subtraction circuit for achieving a subtraction on an input signal to the third 1H delay line and an output signal from the fourth 1H delay line, and a minimum value detecting circuit connected to the first, second, and third subtraction circuits for detecting the minimum value from the subtraction results.

Abstract: A signal converting circuit is disclosed for converting a television signal for 2:1 interlaced scanning system to another television signal for 1:1 non-interlaced scanning system using line memories for storing image data of two adjacent scanning lines of a present field and field memories for storing image data of a last occurring field. An interpolation signal is produced by controlling a value of the televisions signal of the two adjacent scanning lines in response to the television signal of the two adjacent scanning lines in the present field and the television signal of a scanning line positioned between the two adjacent scanning lines in the last occurring field.

Abstract: A video signal processing circuit for producing a still image picture which can be reduced memory capacity. A digital video signal is divided into higher-significant bit and lower-significant bit which are stored in separate addresses of a memory device. The higher-significant bit data is written in the first address. The lower-significant bit data and an identification data signal are written in the following addresses when the present higher-significant bit data is the same as former higher-significant bit data written in the previous address. The lower-significant bit data and a higher-significant bit data of 1 bit are written in the following addresses when the present higher-significant bit data is different from the former higher-significant bit data of the previous address.

Abstract: A D/A converter comprises one or both of a first D/A converter and a second D/A converter. In the first D/A converter, n (n.gtoreq.2) semiconductor devices are connected in parallel to each other between a power supply and a load resistor, gates of (n-1) semiconductor devices (called a first group of semiconductor devices) of the n semiconductor devices are connected to a common gate bias potential source, those semiconductor devices of the first group of semiconductor devices which are equal in number to the number determined by a content of high order bits of an input digital data are turned on to supply a current to the load resistor, and a voltage drop across the load resistor is outputted as an analog quantity representing the high order bits.

Abstract: A transversal filter suitable for use in a ghost canceller of television receiver. The amplifiers of the transversal filter employ MOS transistors each loaded by a complementary connection of a P-MOS transistor and an N-MOS transistor constituting a C-MOS transistor pair.

Abstract: A charge transfer device has one or more charge injection areas each having an input diffusion layer and two or more input gate electrodes. An input signal is applied to the input diffusion layer, a clock voltage is applied to one of the input gates and an input reference voltage is applied to the other input gate to inject a signal charge proportional to a difference between the input reference voltage and the input signal, and the signal charge is sequentially transferred. A magnitude of the input reference voltage is changed in accordance with a magnitude of a maximum value of the input signal so that transfer of charges which do not contribute to signal component is suppressed and a transfer efficiency is improved.

Abstract: An amplifier circuit using MOS transistors. The load to be connected to an amplifying element of the amplifier circuit is formed by a C-MOS transistor having a P-MOS transistor and an N-MOS transistor.

Abstract: A ghost reduction circuit for a television receiver incorporating a transversal filter comprises a memory for storing tap gains of tap gain amplifiers constituting part of the filter, a detector for detecting a ghost component as an error signal by comparing a vertical sync signal of the video signal passed through the filter with a reference sync signal, a circuit for converting a differentiated signal derived through differentiation of the error signal into a 3-state digital signal, and a subtractor for correcting the tap gain data stored in the memory in accordance with the digital signal, wherein the ghost component is substantially eliminated from the video signal inputted to the filter by controlling the gains of the tap gain amplifiers in accordance with the corrected memory data.

Abstract: A wide-band ghost reduction circuit apparatus for a television receiver comprises a ghost detector, two transversal filters having delay characteristics different from each other, a switch for selecting one of the filters and an automatic gain control circuit responsive to the output of the ghost detector for controlling the filters and the switch. Each of the transversal filters includes tap amplifiers whose gains are controlled by the automatic gain control circuit and having outputs connected, respectively, to tap inputs of delay devices formed of such as a CCD each provided with a tap and included in the associated transversal filter. Output end of one of the transversal filters having a smaller delay is connected to a selected one of the input tap of the other transversal filter through a switch so that input video signal components join together at every input terminal or every individual tap position of the delay devices.

Abstract: In a channel selection apparatus for a television receiver or FM radio receiver having an electronic tuner, a local oscillation signal of the electronic tuner having a local oscillator which is swept by a voltage sweeping circuit is passed through a comb-shape filter having a SAW element. Peak outputs from the comb-shape filter are counted by a presettable counter. When the count reaches a preset count, the sweeping operation of the voltage sweeping circuit is stopped to select a desired channel. A portion of the peaks of the comb-shape filter characteristic is attenuated and a gap appearing at the attenuated portion is detected by the frequency sweep of the local oscillation signal with a change in time interval. The detection signal is compared to discriminate the first pulse necessary for the channel selection.

Abstract: A channel indicator suitable for use in a television receiver and an FM receiver each having an electronic tuner is disclosed in which a channel number now being received can be automatically indicated by counting the number of those local oscillation frequencies corresponding to respective channels which the local oscillation frequency of the electronic tuner has passed prior at the arrival to a desired value. Means for compensating for irregular frequency channel intervals and temperature variations are included.

Abstract: A channel selection apparatus comprises a sweep control voltage generator driven by a circuit for sweeping the local oscillation signal frequency in an electronic tuner. The local oscillation signal frequency sweeping circuit includes an arrangement for increasing the rate of sweeping the local oscillation signal frequency only when the latter is being changed not in the vicinity of a destined frequency. The apparatus may further comprise another arrangement for preventing an eventual excessive sweeping beyond the destined frequency.

Abstract: A high-frequency input circuit suitable for use in a television receiver, which includes a tuning circuit which can operate with a reduced loss and can be tuned to signals in, for example, the VHF and UHF bands at the same time. The high-frequency input circuit provides an integrated tuner capable of receiving all the signals within the range from the VHF band to the UHF band.

Abstract: A digital-to-analog converter of a pulse width modulation type in which a single counting cycle of a clock pulse counter is divided into 2.sup.m elementary periods where m represents a selected number of less significant bits of a digital input data to be converted into analog quantity and elementary pulses in number determined in dependence on the logic values of the more significant bits are distributed among the elementary periods, while supplementary elementary pulses are produced in the elementary periods selected in dependence on the logic values of the less significant bits of the digital input data. These elementary pulses are integrated for every elementary period and the integrated output value is converted into a corresponding DC analog output signal.

Abstract: An automatic channel selection apparatus comprises an electronic tuner having a local oscillator an oscillation frequency of which is controlled by an applied voltage, a voltage sweep circuit for sweeping the voltage to be applied to the local oscillator, means for deriving from an output of the local oscillator, signals of different phases and combining those signals, a detector for envelope-detecting an output of the deriving means and means for counting the number of varying cycle periods in the output of the detector which changes periodically each time the oscillation frequency of the local oscillator changes by a given amount which is inversely proportional to the phase difference to change a tuning frequency of the electronic tuner by a specified amount.