Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

Abstract: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.

Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

Abstract: A semiconductor device includes a MIS transistor. The device includes a buried insulating film formed in one part of a substrate, the buried insulating film being elongated in a gate-width direction and shortened in a gate-length direction of the MIS transistor. A first semiconductor layer is formed on the buried insulating film and has uniaxial lattice strain. A second semiconductor layer covers both sides of the buried insulating film and both sides of the first semiconductor layer, the sides being opposite in the gate-length direction. A gate electrode is formed on the first semiconductor layer with a gate insulating film being formed between the gate electrode and the first semiconductor layer. A source region and a drain region are formed in the second semiconductor layer.

Abstract: In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90°. A section perpendicular to the given direction is vertically and horizontally symmetrical.

Abstract: A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

Abstract: A semiconductor device with including a MIS transistor. The device comprises a buried insulating film formed in one part of a substrate, the buried insulating film being elongated in a gate-width direction and shortened in a gate-length direction of the MIS transistor, a first semiconductor layer formed on the buried insulating film and having uniaxial lattice strain, a second semiconductor layer covering both sides of the buried insulating film and both sides of the first semiconductor layer, the sides being opposite in the gate-length direction, a gate electrode formed on the first semiconductor layer with a gate insulating film being formed between the gate electrode and the first semiconductor, and a source region and a drain region which are formed in the second semiconductor layer.

Abstract: A semiconductor device includes a gate-all-around MOSFET structure comprises a first semiconductor layer which is formed on a support substrate and which has a recess formed on a surface thereof, a second semiconductor layer formed on the first semiconductor layer and which has a part thereof formed to cross over the recess of the first semiconductor layer, a gate electrode which is formed through a gate insulation film to surround the crossing portion of the second semiconductor layer and which has parts other than the part located under the second semiconductor layer processed in a gate pattern, source and drain areas formed on the second semiconductor layer, and a sidewall insulation film which is formed on sidewall surfaces of the recess of the first semiconductor layer and which has a greater thickness than the gate insulation film.

Abstract: In a semiconductor device including a full depletion MISFET transistor made by using a SOI layer and intended to stabilize a predetermined threshold value while holding the threshold value sensitivity to fluctuation in thickness of the SOI layer even upon changes in impurity concentration of a channel region of the MISFET transistor by changing a back gate voltage in accordance with the impurity concentration of the channel region, thickness of the SOI layer is determined to reduce changes in threshold value, and impurity concentration of the channel region is measured by using a detector element to adjust the back gate voltage in response to the measured value. Thus, the desired threshold voltage can be maintained.